Dynamic memory programming voltage step for strenuous device conditions
A memory device can dynamically select a voltage step size for programming (i.e., charging) memory cells. The memory device can increase the voltage step size to reduce programming time or decrease the voltage step size to reduce errors. The memory device can identify device conditions, such as temperature or amount of use (e.g., a count of program/erase cycles). The memory device can increase the voltage step size when the device conditions are less likely to cause errors (e.g., in a middle temperature range or below a threshold number of program/erase cycles) or can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., in a high or low temperature range or above a threshold number of program/erase cycles).
1. A method comprising:
identifying device conditions for a memory device;
comparing the device conditions to one or more thresholds to determine whether the memory device is experiencing strenuous device conditions;
when, based on the comparing, the memory device is determined to be experiencing strenuous device conditions, selecting a reduced voltage step size;
when, based on the comparing, the memory device is determined to not be experiencing strenuous device conditions, selecting a standard voltage step size; and
performing a program operation on the memory device, wherein performing the program operation comprises iteratively applying a voltage amount, that is based on the selected voltage step size, until a target charge is achieved.
2. The method of claim 1 ,
wherein the device conditions specify a temperature; and
wherein at least a first one of the one or more thresholds specifies a maximum temperature before the memory device is considered to be experiencing strenuous device conditions and at least a second one of the one or more thresholds specifies a minimum temperature before the memory device is considered to be experiencing strenuous device conditions.
3. The method of claim 1 ,
wherein the device conditions specify a number of program/erase cycles; and
wherein at least one of the one or more thresholds specifies a threshold number of program/erase cycles before the memory device is considered to be experiencing strenuous device conditions.
4. The method of claim 1 ,
wherein the device conditions specify an error rate; and
wherein at least one of the one or more thresholds specifies a threshold error rate before the memory device is considered to be experiencing strenuous device conditions.
5. The method of claim 1 , wherein the method is performed by a controller of the memory device.
6. The method of claim 1 , wherein the memory device is a Negative AND (NAND) memory device.
7. The method of claim 1 , wherein at least one of the one or more thresholds was defined based on a testing procedure performed on a test memory device, other than the memory device, that has a same type as a type of the memory device.
8. The method of claim 1 , wherein at least one of the one or more thresholds was defined based on a testing procedure, performed on the memory device, calibrated to determine how the memory device reacts to extreme heat or cold.
9. The method of claim 1 , wherein at least one of the one or more thresholds was defined based on a testing procedure calibrated to determine how the memory device reacts to program/erase cycles.
10. A non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processing devices, cause the one or more processing devices to:
identify device conditions for a memory device;
apply a mapping of device conditions to voltage step sizes to select a voltage step size corresponding to the identified device conditions; and
performing a program operation on the memory device, wherein performing the program operation comprises iteratively applying a voltage amount, that is based on the selected voltage step size, until a target charge is achieved.
11. The computer-readable storage medium of claim 10 ,
wherein the identified device conditions specify a temperature; and
wherein at least a part of the mapping specifies a temperature range, including the specified temperature, mapped to the selected voltage step size.
12. The computer-readable storage medium of claim 10 ,
wherein the identified device conditions specify a number of program/erase cycles; and
wherein at least a part of the mapping specifies a threshold number of program/erase cycles mapped to the selected voltage step size.
13. The computer-readable storage medium of claim 10 , wherein at least part of the mapping was defined based on a testing procedure, performed on the memory device, calibrated to determine how the memory device reacts to extreme heat or cold.
14. A memory system comprising:
a memory array;
multiple programming voltage step registers, each programming voltage step register storing an indication of a voltage or voltage increment amount; and
a controller configured to select one of the multiple programming voltage step registers based on a determination of conditions of the memory system that correspond to the selected programming voltage step register,
wherein the controller is further configured to perform a program operation on one or more cells in the memory array based on the selected programming voltage step register, wherein performing the program operation comprises iteratively applying a voltage amount that is based on a value stored in the selected programming voltage step register, until a target charge is achieved.
15. The memory system of claim 14 ,
wherein the conditions of the memory system specify a temperature; and
wherein the selection of one of the multiple programming voltage step registers is based on a determination that the specified temperature corresponds to the selected programming voltage step register.
16. The memory system of claim 14 ,
wherein the conditions of the memory system specify a number of program/erase cycles; and
wherein the selection of one of the multiple programming voltage step registers is based on a determination that the specified number of program/erase cycles corresponds to the selected programming voltage step register.
17. The memory system of claim 14 ,
wherein the conditions of the memory system specify an error rate; and
wherein the selection of one of the multiple programming voltage step registers is based on a determination that the specified error rate corresponds to the selected programming voltage step register.
18. The memory system of claim 14 , wherein the correspondence between the conditions of the memory system and the selected programming voltage step register was defined based on a testing procedure performed on a test memory device, other that the memory system, that has a same type as a type of the memory system.
19. The memory system of claim 14 , wherein the correspondence between the conditions of the memory system and the selected programming voltage step register was defined based on a testing procedure, performed on the memory system, calibrated to determine how the memory system reacts to extreme heat or cold.
20. The memory system of claim 14 , wherein the correspondence between the conditions of the memory system and the selected programming voltage step register was defined based on a testing procedure calibrated to determine how the memory system reacts to program/erase cycles.