Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.
1. An array of vertically stacked tiers of memory cells, comprising:
a plurality of horizontally oriented access lines within individual tiers of memory cells;
a plurality of horizontally oriented global sense lines elevationally outward of the tiers of memory cells;
a plurality of select transistors elevationally inward of the tiers of memory cells, individual of the select transistors comprising two source/drain regions;
a plurality of pairs of local first and second vertical lines extending through the tiers of memory cells, the local first vertical line within individual of the pairs being in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors, the local second vertical line within individual of the pairs being in conductive connection with another of the two source/drain regions of the one select transistor;
the local first vertical line being laterally lined with a dielectric material liner and the local second vertical line being laterally lined with a programmable material, the dielectric material having an upper surface elevationally equivalent with an upper surface of the programmable material; and
individual of the memory cells comprising a crossing of the local second vertical lines and one of the horizontal access lines and the programmable material there-between, the programmable material not being in physical contact with the another of the two source/drain regions, the programmable material comprising one or more members of the group consisting of oxide material having ions diffused therein, Sr x Ru y O z , RuO y , In x Sn y O z , BaTiO 3 , Ba (1-x) Sr x TiO 3 , polymer material and memristive material.
2. The array of claim 1 wherein the local first vertical lines are taller than the local second vertical lines.
3. The array of claim 1 , wherein the programmable material further comprises MgO.
4. The array of claim 1 , wherein two of the select transistors comprised by the plurality of select transistors have respective gates that are wired in parallel to selectively enable current flow in each sense line.
5. The array of claim 4 wherein the respective gates are laterally spaced from one another by dielectric material and current conductive material.
6. The array of claim 4 wherein the gates are hard-wired together.
7. The array of claim 4 wherein the gates are soft-wired together.
8. The array of claim 4 wherein the two of the select transistors share a common source/drain region.
9. An array of vertically stacked tiers of memory cells, comprising:
a plurality of horizontally oriented access lines within individual tiers of memory cells;
a plurality of horizontally oriented global sense lines elevationally outward of the tiers of memory cells;
a plurality of select transistors elevationally inward of the tiers of memory cells, individual of the select transistors comprising two source/drain regions;
a plurality of pairs of local first and second vertical lines extending through the tiers of memory cells, the local first vertical line within individual of the pairs being in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors, the local second vertical line within individual of the pairs being in conductive connection with another of the two source/drain regions of the one select transistor;
the local first vertical line being laterally lined with a dielectric material liner and the local second vertical line being laterally lined with a programmable material, the dielectric material having an upper surface elevationally equivalent with an upper surface of the programmable material; and
individual of the memory cells comprising a crossing of the local second vertical lines and one of the horizontal access lines and the programmable material there-between, the programmable material being in non-physical contact with the another of the two source/drain regions.