Reduced footprint fuse circuit

1. A memory device, comprising:

a memory bank accessible via a plurality of memory addresses; and

a fuse array comprising a plurality of fuse banks, wherein a first fuse bank of the plurality of fuse banks comprises a first fuse circuit, wherein the first fuse circuit comprises:

a first fuse latch comprising first input circuitry, wherein the first fuse latch is configured to store a first bit of a first memory address of the plurality of memory addresses received at the first input circuitry; and

a first matching circuit communicatively coupled to the first input circuitry, wherein the first matching circuit is configured to:

receive, at the first input circuitry, a first bit of a second memory address of the plurality of memory addresses; and

output, at output circuitry of the first matching circuit, a first comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.

2. The memory device of claim 1 , wherein the plurality of memory addresses comprises a plurality of row addresses and a plurality of column addresses.

3. The memory device of claim 1 , wherein the first fuse bank comprises a second fuse circuit, wherein the second fuse circuit comprises:

a second fuse latch comprising second input circuitry, wherein the second fuse latch is configured to store a second bit of the first memory address received at the second input circuitry; and

a second matching circuit communicatively coupled to the second input circuitry, wherein the second matching circuit is configured to:

receive, at the second input circuitry, a second bit of the second memory address; and

output, at output circuitry of the second matching circuit, a second comparison result based at least in part on the second bit of the first memory address and the second bit of the second memory address.

4. The memory device of claim 3 , wherein the output circuitry of the first matching circuit and the output circuitry of the second matching circuit are communicatively coupled in parallel.

5. The memory device of claim 3 , wherein the output circuitry of the first matching circuit and the output circuitry of the second matching circuit are communicatively coupled in series.

6. The memory device of claim 3 , wherein the output circuitry of the first matching circuit and the output circuitry of the second matching circuit are both communicatively coupled to a logical AND gate, a logical NAND gate, or a combination thereof.

7. The memory device of claim 1 , wherein the plurality of memory addresses comprises a plurality of redundant memory addresses.

8. The memory device of claim 7 , wherein the first matching circuit is configured to receive the first bit of the second memory address in response to receiving, at the memory device, a command to access the second memory address, and wherein the memory device is configured to access one of the plurality of redundant memory addresses different from the second memory address based at least in part on the first comparison result.

9. The memory device of claim 1 , wherein the memory device comprises a matching line communicatively coupled to a power source of the memory device configured to output a first logical state on the matching line, wherein the output circuitry of the first matching circuit is communicatively coupled to the matching line, and wherein the matching line is configured to transition from the first logical state to a second logical state based at least in part on the first comparison result.

10. The memory device of claim 1 , wherein each of the plurality of fuse banks corresponds to a respective address of the plurality of memory addresses.

11. The memory device of claim 1 , wherein the memory device is a double data rate type five (DDR5) memory device.

12. A method, comprising:

receiving, at first input circuitry, a first bit of a first memory address of a plurality of memory addresses of a memory device;

latching, at a first fuse latch communicatively coupled to the first input circuitry, the first bit of the first memory address;

receiving, at the first input circuitry, a first bit of a second memory address of the plurality of memory addresses;

determining, at a first matching circuit communicatively coupled to the first input circuitry, a first comparison result based at least in part on the first bit of the first memory address and the second bit of the second memory address, wherein the first matching circuit is configured to receive the first bit of the first memory address from the first fuse latch; and

outputting, at output circuitry of the first matching circuit, the first comparison result.

13. The method of claim 12 , comprising receiving the first bit of the first memory address after determining the first memory address is inoperative.

14. The method of claim 12 , comprising receiving the first bit of the second memory address at the first matching circuit after receiving, at the memory device, a command to access the second memory address.

15. The method of claim 12 , comprising latching, at the first fuse latch, the first bit of the first memory address in response to identifying, at second input circuitry communicatively coupled to the first fuse latch, a transition of a latch signal from a first logical state to a second logical state.

16. The method of claim 15 , comprising transitioning the latch signal from the first logical state to the second logical state during an initialization of the memory device.

17. A system, comprising:

a first fuse latch comprising first input circuitry, wherein the first fuse latch is configured to store a first bit of a first memory address of a plurality of memory addresses of a memory bank received at the first input circuitry, wherein the first memory address comprises an inoperative memory address of the memory bank; and

a first matching circuit communicatively coupled to the first input circuitry, wherein the first matching circuit is configured to:

receive, at the first input circuitry, a first bit of a second memory address of the plurality of memory addresses; and

output, at output circuitry of the first matching circuit, a first comparison result based at least in part on a comparison of the first bit of the first memory address and the first bit of the second memory address.

18. The system of claim 17 , wherein the first bit of the first memory address comprises a first bit of a third memory address of the plurality of memory addresses, wherein the third memory address comprises an additional inoperative memory address of the memory bank.

19. The system of claim 18 , comprising a first fuse bank and a second fuse bank, wherein the first fuse bank comprises the first fuse latch and the first matching circuit, wherein the second fuse bank comprises:

a second fuse latch comprising second input circuitry, wherein the second fuse latch is configured to store a second bit of the third memory address received at the second input circuitry; and

a second matching circuit communicatively coupled to the second input circuitry, wherein the second matching circuit is configured to:

receive, at the second input circuitry, a second bit of the second memory address; and

output, at output circuitry of the second matching circuit, a second comparison result based at least in part on additional comparison of the second bit of the third memory address and the second bit of the second memory address.

20. The system claim 17 , wherein the first matching circuit comprises a multiplexer.