Source line management for memory cells with floating gates
View Patent ↗Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.
1. An apparatus, comprising:
an array of memory cells, each memory cell of the array of memory cells comprising a first transistor that includes a control gate and a floating gate and a second transistor connected with the floating gate of the first transistor, wherein each memory cell is configured to store a logic state using the first transistor and second transistor;
a plurality of word lines, each word line connected with control gates of the first transistors and gates of the second transistors of memory cells of a row of the array;
a plurality of digit lines, each digit line connected with a first node of the first transistors and a second node of the second transistors of memory cells of a column of the array; and
a plurality of source lines, each source line corresponding to one digit line of the plurality of digit lines and connected with a second node of the first transistor of a respective memory cell that is connected with the one digit line, each source line configured to be biased based on an operation being performed using the one digit line.
2. The apparatus of claim 1 , further comprising:
a clamp row of memory cells coupled with the array of memory cells, each memory cell of the clamp row of memory cells comprising a third transistor that includes a floating gate and a fourth transistor connected with the floating gate of the third transistor, wherein a first node of each of the third transistors is connected with a corresponding source line of the plurality of source lines; and
a clamp line connected with a control gate of each of the third transistors and configured to bias the corresponding source line to a voltage of the one digit line based on the operation being a write operation.
3. The apparatus of claim 2 , wherein a second node of each of the third transistors is connected with the corresponding one digit line.
4. The apparatus of claim 2 , wherein the clamp line is configured to bias the corresponding source line to the voltage of the one digit line by activating the each of the third transistors to couple the corresponding source line with the one digit line.
5. The apparatus of claim 2 , wherein a third node of each of the fourth transistors is connected with the corresponding one digit line and a gate of each of the fourth transistors is connected with the clamp line.
6. The apparatus of claim 1 , further comprising:
a ground row of memory cells coupled with the array of memory cells, each memory cell of the ground row of memory cells comprising a fifth transistor that includes a floating gate and a sixth transistor coupled with the floating gate of the fifth transistor, wherein a first node of each of the fifth transistors is connected with a corresponding source line of the plurality of source lines; and
a ground line connected with a control gate of each of the fifth transistors and configured to bias the corresponding source line to a ground voltage based on the operation being a read operation.
7. The apparatus of claim 6 , wherein a second node of each of the fifth transistors is connected with the ground voltage.
8. The apparatus of claim 6 , wherein the ground line is configured to bias the corresponding source line to the ground voltage by activating the each of the fifth transistors to couple the corresponding source line with the ground voltage.
9. The apparatus of claim 1 , wherein the first transistor of each memory cell is a p-type transistor and the second transistor of each memory cell is an n-type transistor.