Compensating for memory input capacitance
View Patent ↗Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).
1. An apparatus, comprising:
a substrate;
an access line comprising a first portion in contact with the substrate and a second portion;
a memory die coupled with the substrate via the second portion of the access line;
a memory controller coupled with the access line and configured to transmit, through the access line to the memory die, a signal having an amplitude level and modulated with a modulation scheme having at least two levels; and
an inductive region coupled with the access line and configured to change a first noise level associated with the amplitude level of the signal to a second noise level based at least in part on altering a capacitance of the access line.
2. The apparatus of claim 1 , wherein the access line further comprises:
a third portion coupled with the inductive region and located between the substrate and the memory die.
3. The apparatus of claim 2 , wherein the inductive region is located between the substrate and the memory die.
4. The apparatus of claim 3 , wherein the third portion of the access line is coupled with the first portion of the access line.
5. The apparatus of claim 1 , further comprising:
a metal layer coupled with the second portion of the access line and the memory die, the second portion of the access line coupled with the memory die via the metal layer.
6. The apparatus of claim 5 , wherein the metal layer comprises a die pad coupled with the inductive region.
7. The apparatus of claim 1 , wherein the first portion of the access line comprises a first segment and a second segment that is orthogonal to the first segment.
8. The apparatus of claim 1 , wherein at least a portion of the inductive region is in contact with the substrate.
9. The apparatus of claim 1 , wherein the first portion of the access line comprises a first segment that is orthogonal to the second portion of the access line.
10. An apparatus, comprising:
a substrate;
an access line coupled with the substrate;
an inductive region coupled with the access line and configured to alter a capacitance of the access line;
a memory die coupled with the substrate via the access line and configured to receive a signal having a second noise level; and
a memory controller coupled with the access line and configured to:
generate the signal having an amplitude level and using a modulation scheme having at least two levels; and
transmit the signal to the memory die through the inductive region, wherein the inductive region is configured to change a first noise level associated with the amplitude level of the signal to the second noise level based at least in part on altering the capacitance of the access line.
11. The apparatus of claim 10 , wherein the inductive region is configured to filter the signal based at least in part on the signal being transmitted, and wherein the signal comprises the second noise level based at least in part on the filtering.
12. The apparatus of claim 10 , wherein the access line comprises a first portion coupled with the substrate and a second portion coupled with the memory die, the first portion of the access line orthogonal to the second portion of the access line.
13. The apparatus of claim 12 , wherein the access line further comprises:
a third portion located between the substrate and the memory die and configured to transmit the signal to a memory cell of the memory die.
14. The apparatus of claim 13 , wherein a bottom surface of the inductive region is located below an upper surface of the substrate.
15. The apparatus of claim 10 , wherein the inductive region is coil-shaped and is coupled with the substrate and the memory die.
16. The apparatus of claim 10 , wherein the access line comprises a redistribution layer (RDL) or an inline redistribution layer (iRDL) and is coupled with a die pad of the memory die.
17. A method comprising:
receiving, at an access line of a memory device, a signal having an amplitude level and a first noise level associated with the amplitude level, the access line coupled with a substrate, an inductive region, and a memory die;
changing, via the inductive region, the first noise level associated with the amplitude level of the signal to a second noise level different than the first noise level based at least in part on the inductive region altering a capacitance of the access line; and
receiving the signal at a memory cell of the memory die based at least in part on changing the first noise level, the received signal comprising the second noise level different than the first noise level.
18. The method of claim 17 , wherein altering the capacitance of the signal comprises:
filtering, at the inductive region, the signal based at least in part on transmitting the signal, the signal comprising the second noise level based at least in part on the filtering.
19. The method of claim 17 , wherein altering the capacitance of the access line comprises:
altering the capacitance of the access line from the first noise level down to the second noise level.
20. The method of claim 17 , wherein the signal is modulated with a modulation scheme having at least three levels.