IP Library Granted Patent US 10,983,890
Granted Patent B2
US 10,983,890 · App. 16/154,842 · Granted Apr 20, 2021

Real time trigger rate monitoring in a memory sub-system

Inventor: Francis Chew (Boulder, CO)
Assignee: Micron Technology, Inc.
G06F11/3037G06F11/1068G06F11/3058G06F11/3476
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,983,890
App. No.
16/154,842
Granted
Apr 20, 2021
Kind
B2
Abstract

The rate at which reads on a target memory portion initiate error recovery procedures can be monitored in real-time. Trigger rates can be used to perform analysis of a memory sub-system or to implement improvements in the memory sub-system. Trigger rate monitoring can include accessing a count of error recovery initializations for a target memory portion, wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-stage error recovery process was performed. Trigger rate monitoring can further include accessing a count of read operations corresponding to the target memory portion. The count of error recovery initializations and the count of read operations can be used to compute a trigger rate. The trigger rate, or multiple trigger rates from various times or from various target memory portions, can be used to compute a metric for the memory portion(s).

Claims (61)

1. A method comprising:

accessing a count of error recovery initializations for a target memory portion, wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-stage error recovery process was performed;

accessing a count of read operations corresponding to the target memory portion;

computing a trigger rate for the target memory portion based at least in part on the count of error recovery initializations and the count of read operations; and

saving the trigger rate for the target memory portion to a trigger rate log,

wherein the target memory portion is a first target memory portion; and

wherein the method further comprises:

accessing multiple trigger rates stored in the trigger rate log;

identifying one or more first trends for the multiple trigger rates;

comparing the first trends to one or more second trends identified in relation to a second target memory portion; and

adjusting the first memory portion or the second memory portion based on the comparison.

2. The method of claim 1 , wherein the method is initiated in response to a start condition for trigger rate sampling comprising a timer reaching a threshold.

3. The method of claim 1 , wherein the target memory portion is a die.

4. The method of claim 3 , wherein accessing the count of read operations comprises accessing a counter corresponding to a number of code word reads on a per-die basis.

5. The method of claim 1 , wherein computing the trigger rate comprises dividing the count of error recovery initializations by the count of read operations.

6. The method of claim 1 , wherein the trigger rate is saved to the trigger rate log in association with meta-data specifying a timestamp or a temperature of the target memory portion.

7. The method of claim 1 , further comprising computing a metric for the target memory portion based at least in part on the computed trigger rate and one or more previously-computed trigger rates for the target memory portion, wherein computing the metric for the target memory portion comprises one or more of computing: a maximum trigger rate, a minimum trigger rate, or a slope of a function fit to multiple trigger rates from among the group comprising both the computed trigger rate and the previously-computed trigger rates.

8. The method of claim 7 further comprising setting a frequency of a background scan for the memory portion based on the computed metric.

9. A non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processing devices, cause the one or more processing devices to:

identify a start condition for trigger rate sampling;

access a count of error recovery initializations for a target memory portion;

access a count of read operations corresponding to the target memory portion;

compute a trigger rate for the target memory portion based at least in part on the count of error recovery initializations and the count of read operations; and

save the trigger rate for the target memory portion to a trigger rate log,

wherein the target memory portion is a first target memory portion; and

wherein the operations further comprise:

accessing multiple trigger rates stored in the trigger rate log;

identifying one or more first trends for the multiple trigger rates;

comparing the first trends to one or more second trends identified in relation to a second target memory portion; and

adjusting the first memory portion or the second memory portion based on the comparison.

10. The computer-readable storage medium of claim 9 , wherein the start condition for trigger rate sampling is receiving a command from a user.

11. The computer-readable storage medium of claim 9 , wherein the operations further comprise:

computing a metric based at least in part on the multiple trigger rates;

comparing the metric to a threshold; and

based on the comparison, identifying the target memory portion as being a bottleneck in a memory device.

12. The computer-readable storage medium of claim 9 , wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-state error recovery process was performed.

13. The computer-readable storage medium of claim 9 , wherein the operations further comprise:

determining that the target memory portion failed and in response:

computing a metric that compares trigger rates earlier in the trigger rate log to those leading up to the identified failure.

14. The computer-readable storage medium of claim 13 , wherein the operations further comprise setting a frequency of a background scan for the target memory portion based on the computed metric.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, configured to:

access a count of error recovery initializations for a target memory portion of the memory device;

access a count of read operations corresponding to the target memory portion;

compute a trigger rate for the target memory portion based at least in part on the count of error recovery initializations and the count of read operations; and

save the trigger rate for the target memory portion to a trigger rate log,

wherein the target memory portion is a first target memory portion; and

wherein the processing device is further configured to:

access multiple trigger rates stored in the trigger rate log;

identify one or more first trends for the multiple trigger rates;

compare the first trends to one or more second trends identified in relation to a second target memory portion; and

adjust the first memory portion or the second memory portion based on the comparison.

16. The system of claim 15 , wherein the count of read operations is a count of code word read operations.

17. The system of claim 15 ,

wherein accessing the count of error recovery initializations comprises accessing a count of error recovery initializations within a specified timeframe; and

wherein accessing the count of read operations comprises accessing a count of code word reads within the specified timeframe.

18. The system of claim 15 , wherein the processing device is further configured to:

divide the multiple trigger rates into groups based on timestamps associated with each trigger rate; and

identify a trend for each of one or more of the groups of the trigger rates.

19. The system of claim 15 , wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-stage error recovery process was performed.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2021
From: MIDWEST CONCRETE MASONRY & SUPPLY INC.
To: CCS CONTRACTOR EQUIPMENT & SUPPLY, INC.
Reel/Frame 056313/0471 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2018
From: CHEW, FRANCIS
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047774/0040 →
Continuity (1)
Related Publication 20200110685A1 · Apr 9, 2020