IP Library Granted Patent US 10,930,499
Granted Patent B2
US 10,930,499 · App. 16/379,085 · Granted Feb 23, 2021

Semiconductor structure formation

Inventors: Nicholas R. Tapias (Boise, ID); Sanjeev Sapra (Boise, ID); Anish A. Khandekar (Boise, ID); Shen Hu (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/02636H01L21/02381H01L21/02428H01L21/02532H01L21/02592H01L21/76224H01L21/823821
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Quick Facts
Patent No.
US 10,930,499
App. No.
16/379,085
Granted
Feb 23, 2021
Kind
B2
Abstract

Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

Claims (21)

1. A method, comprising:

forming a silicon (Si) material on a semiconductor substrate;

forming an opening through the silicon (Si) material to a first depth to form pillars of the Si material;

depositing an isolation material within the opening to fill the opening between the Si pillars;

removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars; and

depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

2. The method of claim 1 , wherein the method further comprises:

initially depositing the isolation material about the Si material having an initial height such that:

the top portion of the isolation material is positioned over top portions of the pillars,

the isolation material extends along outer sidewalls of the pillars from the top portion of the isolation material to the semiconductor substrate, and

the isolation material extends within the opening between the pillars along the inner sidewalls of the pillars from the top portion of the isolation material to a bottom portion of the opening.

3. The method of claim 2 , wherein the method further comprises:

subsequently removing the isolation material about the Si material to have a subsequent height less than the initial height to form an exposed area of the pillars extending a predetermined distance from the top portions of the pillars to the top portion of the isolation material.

4. The method of claim 3 , wherein the method further comprises depositing the enhancer material to be positioned along the exposed area of the pillars.

5. The method of claim 4 , wherein the method further comprises depositing the enhancer material to have a predetermined width less than one half of a width extending between the inner sidewalls of the pillars.

6. The method of claim 5 , wherein the method further comprises depositing the enhancer material to be positioned along the top portion of the isolation material and to extend above the isolation material between the inner sidewalls of the pillars, and between the outer sidewalls of the pillars and outer sidewalls of the isolation material.

7. The method of claim 6 , wherein the method further comprises:

removing a first portion of the enhancer material along a top portion of the isolation material extending between outer sidewalls of the enhancer material positioned within the opening along the inner sidewalls of the pillars; and

removing a second portion of the enhancer material along the top portion of the isolation material extending between the outer sidewalls of the enhancer material positioned along outer sidewalls of the pillars and the outer sidewalls of the isolation material.

8. The method of claim 1 , wherein the isolation material comprises silicon oxide.

9. The method of claim 1 , wherein the enhancer material comprises one of amorphous silicon, amorphous geranium, amorphous silicon geranium, amorphous boron-doped silicon geranium, phosphorous-doped a-silicon, arsenic-doped a-silicon, and indium-doped a-silicon.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2019
From: TAPIAS, NICHOLAS R.; SAPRA, SANJEEV; KHANDEKAR, ANISH A.; HU, SHEN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048833/0486 →