IP Library Granted Patent US 10,970,222
Granted Patent B2
US 10,970,222 · App. 16/289,510 · Granted Apr 6, 2021

Eviction of a cache line based on a modification of a sector of the cache line

Inventors: Dhawal Bavishi (San Jose, CA); Robert M. Walker (Raleigh, NC)
Assignee: Micron Technology, Inc.
G06F12/0891G06F2212/1032
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Quick Facts
Patent No.
US 10,970,222
App. No.
16/289,510
Granted
Apr 6, 2021
Kind
B2
Abstract

An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.

Claims (44)

1. A method comprising:

receiving an indication to perform an eviction operation on a cache line in a cache;

determining whether at least one sector of a plurality of sectors of the cache line to be evicted is associated with invalid data having an associated logical address;

in response to determining that at least one sector of the plurality of sectors of the cache line to be evicted is associated with invalid data, performing, by a processing device, a read operation to retrieve, from a storage location outside the cache, valid data associated with the at least one sector and having a same logical address as the invalid data;

modifying the at least one sector of the cache line to be evicted that is associated with the invalid data based on the valid data, wherein modifying the at least one sector comprises replacing the invalid data in the at least one sector of the cache line to be evicted with the retrieved valid data having the same logical address; and

performing the eviction operation on the cache line with the modified at least one sector.

2. The method of claim 1 , wherein the performing of the eviction operation on the cache line with the modified at least one sector corresponds to writing data of the plurality of sectors of the modified cache line to one or more memory components.

3. The method of claim 1 , wherein the read operation is performed at one or more memory components, and wherein the eviction operation stores data of the cache line at the one or more memory components.

4. The method of claim 1 , wherein performing the read operation to retrieve the valid data associated with the at least one sector comprises:

determining that the valid data is stored in a second cache; and

performing the read operation on the second cache to obtain the valid data for the at least one sector, and wherein the eviction operation stores data of the cache line at one or more memory components associated with a backing store.

5. The method of claim 1 , wherein the cache line is selected from a plurality of cache lines in the cache.

6. The method of claim 5 , wherein the cache line is selected based on the cache line being a least recently used cache line of the plurality of cache lines in the cache.

7. The method of claim 1 , wherein each sector of the plurality of sectors of the cache line corresponds to data associated with one or more read operations or one or more write operations.

8. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

receive an indication to perform an eviction operation on a cache line in a cache;

determine that a portion of the cache line to be evicted is associated with invalid data having an associated logical address;

in response to determining that the portion of the cache line to be evicted is associated with invalid data, determine whether a second cache includes valid data for the portion of the cache line that is associated with the invalid data and has a same logical address as the invalid data;

retrieve the valid data from the second cache in response to determining that the second cache includes the valid data;

replace the invalid data at the portion of the cache line to be evicted with the retrieved valid data having the same logical address; and

perform the eviction operation on the cache line in the cache based on the retrieved valid data.

9. The system of claim 8 , wherein the cache is a write-read cache and the second cache is a read-only cache.

10. The system of claim 9 , wherein the write-read cache stores data from a host system in response to the host system being associated with a first workload, and wherein the read-only cache stores data from the host system in response to the host system being associated with a different second workload.

11. The system of claim 8 , wherein the processing device is further to:

retrieve the valid data from a backing store in response to determining that the second cache does not include the valid data.

12. The system of claim 8 , wherein

the eviction operation is performed on the cache line with the retrieved valid data that has replaced the invalid data.

13. The system of claim 8 , wherein the cache line is selected from a plurality of cache lines based on the cache line being a least recently used cache line of the plurality of cache lines in the cache.

14. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

receiving an indication to perform an eviction operation on a cache line in a cache;

determining whether at least one sector of a plurality of sectors of the cache line to be evicted is associated with invalid data having an associated logical address;

in response to determining that at least one sector of the plurality of sectors of the cache line to be evicted is associated with invalid data, performing a read operation to retrieve, from a storage location outside the cache, valid data associated with the at least one sector and having a same logical address as the invalid data;

modifying the at least one sector of the cache line to be evicted that is associated with the invalid data based on the valid data, wherein modifying the at least one sector comprises replacing the invalid data in the at least one sector of the cache line to be evicted with the retrieved valid data having the same logical address; and

performing the eviction operation on the cache line with the modified at least one sector.

15. The non-transitory computer readable medium of claim 14 , wherein the performing of the eviction operation on the cache line with the modified at least one sector corresponds to writing data of the plurality of sectors of the modified cache line to one or more memory components.

16. The non-transitory computer readable medium of claim 14 , wherein the read operation is performed at one or more memory components, and wherein the eviction operation stores data of the cache line at the one or more memory components.

17. The non-transitory computer readable medium of claim 14 , wherein to perform the read operation to retrieve the valid data associated with the at least one sector, the operations further comprise:

determining that the valid data is stored in a second cache; and

performing the read operation on the second cache to obtain the valid data for the at least one sector, and wherein the eviction operation stores data of the cache line at one or more memory components associated with a backing store.

18. The non-transitory computer readable medium of claim 14 , wherein the cache line is selected from a plurality of cache lines in the cache.

19. The non-transitory computer readable medium of claim 18 , wherein the cache line is selected based on the cache line being a least recently used cache line of the plurality of cache lines in the cache.

20. The non-transitory computer readable medium of claim 14 , wherein each sector of the plurality of sectors of the cache line corresponds to data associated with one or more read operations or one or more write operations.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2019
From: BAVISHI, DHAWAL; WALKER, ROBERT M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048472/0932 →