Memory disablement for data security
View Patent ↗Apparatuses and methods related to memory disablement for memory security. Disabling the memory for memory security can include, responsive to receiving a trigger signal, provide a voltage, which may be in excess of an operating or nominal voltage, to the access circuitry. The voltage may thus be sufficient to render the access circuitry inoperable for accessing data stored in the memory array.
1. An apparatus, comprising:
a memory array;
access circuitry coupled to the memory array and configured to operate at a first nominal voltage and provide access to data stored therein;
additional circuitry coupled to the access circuitry and configured to, responsive to receiving a trigger signal, provide a second nominal voltage to the access circuitry, the second nominal voltage being greater than the first nominal voltage and greater than a rated voltage for the access circuitry; and
redundant access circuitry to regain access to the data stored in the memory array subsequent to the access circuitry being damaged via an application of the second nominal voltage to the access circuitry.
2. The apparatus of claim 1 , wherein the apparatus is a memory device, and wherein the additional circuitry is on die with the access circuitry and the memory array.
3. The apparatus of claim 1 , wherein the apparatus comprises a memory module, wherein the access circuitry is on a die with the memory array, and wherein the additional circuitry is separate from the die comprising the memory array.
4. The apparatus of claim 3 , wherein the memory module comprises an interface to couple to a host.
5. The apparatus of claim 1 , wherein the access circuitry is coupled to the memory array.
6. The apparatus of claim 1 , wherein the additional circuitry comprises a voltage pump.
7. The apparatus of claim 6 , wherein the voltage pump is deactivated to prevent the access circuitry from being made inoperable responsive to the additional circuitry.
8. The apparatus of claim 1 , further comprising a controller configured to provide the trigger signal to the additional circuitry responsive to at least one of:
a threshold amount of measured gamma rays;
a threshold amount of measured radio waves; or
a threshold amount of measured light; or
any combination thereof.
9. The apparatus of claim 8 , further comprising a memory module, and wherein the controller is external to the memory module and coupled thereto via an interface.
10. The apparatus of claim 1 , wherein the access circuitry comprises column select circuitry.
11. The apparatus of claim 1 , wherein the access circuitry comprises at least one of row driver circuitry and refresh circuitry.
12. The apparatus of claim 1 , further comprising a controller configured to provide the trigger signal to the additional circuit responsive to receiving a signal from a host.
13. The apparatus of claim 1 , wherein the apparatus is a system comprising a host coupled to a memory device comprising the memory array, the access circuitry, and the additional circuit, and wherein a circuitry configured to provide the trigger signal to the kill circuit is independent of the host and a controller of the memory device.
14. A method comprising:
providing an operating voltage to first circuitry of a memory device in association with accessing data stored in a memory array of the memory device;
responsive to a trigger event, enabling, via a trigger signal, second circuitry of the memory device in order to provide an over-voltage to the first circuitry to render the first circuitry inoperable for accessing the data stored in the memory array; and
regaining, via redundant access circuitry, access to the data stored in the memory array of the memory device subsequent to the first circuitry being damaged via an application of the over-voltage to the first circuitry.
15. The method of claim 14 , wherein the over-voltage is sufficient to disable at least a portion of the first circuitry, and wherein the method comprises providing the over-voltage to the first circuitry from a voltage pump on die with the memory device.
16. The method of claim 14 , wherein, the over-voltage is different from the operating voltage.
17. The method of claim 16 , wherein the over-voltage is higher than the operating voltage.
18. The method of claim 14 , wherein the over-voltage and the operating voltage are provided by a same source.
19. A system comprising:
a host; and
a memory device coupled to the host and comprising:
a voltage pump;
a memory array; and
access circuitry configured to access data stored in the memory array; and
redundant access circuitry;
wherein the memory device is configured to, responsive to a command from the host, provide a trigger signal to a transistor to provide a voltage generated by the voltage pump to the access circuitry in order to damage the access circuitry sufficiently to render it inoperable for accessing the memory array; and
wherein the memory device is configured to activate the redundant access circuitry to regain access to the data stored in the memory array subsequent to the access circuitry being damaged via the application of the voltage generated by the voltage pump.
20. The system of claim 19 , wherein the memory device is further configured to, responsive to a different command from the host, provide a different trigger signal to a different transistor to provide the voltage generated by the voltage pump to the redundant access circuitry in order to damage the redundant access circuitry sufficiently to render it inoperable for accessing the memory array.