Deferred error code correction with improved effective data bandwidth performance
A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.
1. A method comprising:
starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition;
receiving an operation from a processor during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system;
executing the operation and issuing a command to a memory bank of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache;
returning a result of the command to the processor while the ECC data is present in the local cache;
detecting an end of the deferred period of operation; and
executing the ECC operations after the end of the deferred period.
2. The method of claim 1 , the detecting the satisfaction of the condition comprising detecting one of:
a receipt of a second command to start the deferred period from the processor; or
a data bus utilization above a predetermined threshold.
3. The method of claim 1 , the detecting the end of the deferred period comprising detecting one of:
a receipt of a third command to stop the deferred period from the processor;
a data bus utilization below a predetermined threshold; or
the local cache is full.
4. The method of claim 1 , the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
5. The method of claim 4 , the executing the ECC operations comprising writing the ECC parity bits to the memory bank using the address.
6. The method of claim 1 , the operation comprising a read operation and the generating ECC data comprising:
generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
7. The method of claim 5 , the executing the ECC operations comprising:
detecting a mismatch using the ECC syndrome; and
in response to detecting the mismatch, alerting the processor that an error executing the read operation occurred.
8. A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining the steps of:
starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition;
receiving an operation from a host processor during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system;
executing the operation and issuing a command to a memory bank of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache;
returning a result of the command to the host processor while the ECC data is present in the local cache;
detecting an end of the deferred period of operation; and
executing the ECC operations after the end of the deferred period.
9. The non-transitory computer-readable storage medium of claim 8 , the detecting the satisfaction of the condition comprising detecting one of;
a receipt of a second command to start the deferred period from the host processor; or
a data bus utilization above a predetermined threshold.
10. The non-transitory computer-readable storage medium of claim 8 , the detecting the end of the deferred period comprising detecting one of:
a receipt of a third command to stop the deferred period from the host processor;
a data bus utilization below a predetermined threshold; or
the local cache is full.
11. The non-transitory computer-readable storage medium of claim 8 , the operation comprising a write operation and the generating ECC comprising:
generating ECC parity bits based on the. data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
12. The non-transitory computer-readable storage medium of claim 11 , the executing the ECC operations comprising writing the ECC parity bits to the memory bank using the address.
13. The non-transitory computer-readable storage medium of claim 8 , the operation comprising a read operation and the generating ECC data comprising:
generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
14. The non-transitory computer-readable storage medium of claim 13 , the executing the ECC operations comprising:
detecting a mismatch using the ECC syndrome; and
in response to detecting the mismatch, alerting the host processor that an error executing the read operation occurred.
15. A memory system comprising:
a plurality of memory banks;
a bus connected to the memory banks; and
a controller connected to the bus, the controller configured to perform the operations of:
starting a deferred period of operation from a processor of the memory system in response to detecting the satisfaction of a condition;
receiving an operation during the deferred period, the operation comprising a read or write operation access the memory banks;
executing the operation and issuing a command to the memory banks of the memory system, wherein the command does not include error code correction (ECC) data;
generating ECC data prior to receiving a response to the command from the memory bank;
caching the ECC data in a local cache;
returning a result of the command to the processor while the ECC data is present in the local cache;
detecting an end of the deferred period of operation; and
executing the ECC operations after the end of the deferred period.
16. The memory system of claim 15 , the detecting the satisfaction of the condition comprising detecting one of:
a receipt of a second command to start the deferred period from the processor; or
a data utilization of the bus above a predetermined threshold.
17. The memory system of claim 15 , the detecting the end of the deferred period comprising detecting one of:
a receipt of a third command to stop the deferred period from the processor;
a data utilization of the bus below a predetermined threshold; or
the local cache is full.
18. The memory system of claim 15 , the operation comprising a write operation and the generating ECC data comprising:
generating ECC parity bits based on data in the write operation; and
storing the ECC parity bits and an address associated with the data in the local cache.
19. The memory system of claim 18 , the executing the ECC operations comprising writing the ECC parity bits to the memory bank using the address.
20. The memory system of claim 15 , the operation comprising a read operation and the generating ECC data comprising:
generating an ECC syndrome based on data in the read operation; and
storing the ECC syndrome and an address associated with the data in the local cache.
21. The memory system of claim 20 , the executing the ECC operations comprising:
detecting a mismatch using the ECC syndrome; and
in response to detecting the mismatch, alerting a processor that an error executing the read operation occurred.