IP Library Patent Application 16226119
Patent Application
App. No. 16/226,119

MODULE PROCESSING RESOURCE

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
16/226,119
Abstract

The present disclosure includes apparatuses and methods related to a module processing resource. An example apparatus can include a first interface coupled to a host, and a second interface coupled to a memory module. The apparatus may be configured to process data between the host and the memory module via a processing resource.

Claims (30)

1 . An apparatus, comprising:

a processing resource configured to process data transferred between a memory module and a host that comprises at least one of a central processing unit (CPU), graphics processing unit (GPU), or a general purpose GPU (GPGPU), or any combination thereof

a first interface coupled to the processing resource and couplable to the host; and

a second interface coupled to the processing resource and couplable to the memory module.

2 . The apparatus of claim 1 , wherein the processing resource is configured to reorder data from the host for storage on the memory module.

3 . The apparatus of claim 1 , wherein the processing resource is configured to filter the data read from the memory module to the host.

4 . The apparatus of claim 1 , wherein the first interface is couplable to the host via a first bus and wherein the first bus is located on a PCB.

5 . The apparatus of claim 1 , wherein the second interface is couplable to the memory module via a second bus and wherein the second bus is located off a PCB.

6 . The apparatus of claim 1 , wherein the first interface is configured for a first communication protocol and the second interface is a configured for a second communication protocol that is different from the first communication protocol.

7 . The apparatus of claim 6 , wherein the first interface is configured for at least one of NVDIMM-P, NVDIMM-N, DDR5, or DDR4, or any combination thereof.

8 . The apparatus of claim 6 , wherein the second interface is configured to write data to or read data from a 3D XPoint array.

9 . A system, comprising:

a first memory module with a first interface, a second interface, and a first processing resource;

a host including a third interface, wherein the host is coupled to the first memory module via the first interface, the third interface, and a first bus; and

a second memory module including a fourth interface, wherein the second memory module is coupled to the first memory module via the second interface, the fourth interface, and a second bus; and wherein the first processing resource is configured to process data for storage on the first memory module.

10 . The system of claim 9 , wherein the first processing resource is configured to process data for storage on the second memory module.

11 . The system of claim 9 , wherein the second memory module includes a second processing resource.

12 . The system of claim 11 , wherein the second processing resource is configured to process data for storage on the second memory module.

13 . The system of claim 11 , wherein the second processing resource is configured to process data for storage on the first memory module.

14 . The system of claim 9 , wherein the first processing resource is configured to process data by reordering the data and sending the reordered data to the second memory module via the second interface, the fourth interface, and the second bus.

15 . The system of claim 9 , wherein the first processing resource is configured to process data by reordering the data and sending the reordered data to the second memory module via the first interface, the third interface, and the first bus.

16 . The system of claim 9 , wherein the second processing resource is configured to process data by reordering the data and sending the reordered data to the first memory module via the second interface, the fourth interface, and the second bus.

17 . A method, comprising:

receiving, at a processing resource on a first module, a command from a host device that comprise one or more processing units;

reading data from or writing data to a second module that comprises one or more memory dies in response to receiving the commands; and

processing the data read from or written to dies of the second module with the processing resource based on instructions in the command.

18 . The method of claim 17 , further including storing the processed data on the memory module that includes the processing resource.

19 . The method of claim 17 , wherein storing the processed data includes transferring the processed data from a module that includes the processing resource to the memory module.

20 . The method of claim 17 , wherein processing the data includes reordering the data and further including storing the reordered data on the memory module.

21 . The method of claim 17 , further including receiving the command from a host at a module that includes the processing resource.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2018
From: WALKER, ROBERT M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047820/0595 →