Memory arrays
Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.
1. An apparatus, comprising:
a semiconductor-material fin, wherein the semiconductor-material fin comprises a first pedestal serving as a first source/drain region, a second pedestal serving as a second source/drain region, and a first trough defining a first channel region between the first and second source/drain regions, the first and second source/drain regions and the channel region being arranged in line in a first direction;
a first conductive trunk line extending in a second direction crossing the first direction; and
a first conductive branch line branching from the first conductive trunk line and extending in the first direction such that a portion of the first conductive branch line overlaps the first channel region with an intervention of first gate dielectric material to serve as a first gate.
2. The apparatus of claim 1 ,
wherein the first direction crosses the second direction with an angle other than 90°.
3. The apparatus of claim 1 ,
wherein an upper surface of each of the first conductive trunk line and the first conductive branch line is lower than an upper surface of each of the first and second source/drain regions.
4. The apparatus of claim 1 ,
wherein the semiconductor-material fin further comprises a third pedestal serving as a third source/drain region and a second trough defining a second channel region between the second and third source/drain regions, the first, second and third source/drain regions and the first and second channel regions being arranged in line in the first direction; and
wherein the apparatus further comprises:
a second conductive trunk line extending in the second direction; and
a second conductive branch line branching from the second conductive trunk line and extending in the first direction such that a portion of the second conductive branch line overlaps the second channel region with an intervention of second gate dielectric material to serve as a second gate.
5. The apparatus of claim 4 ,
wherein the first direction crosses the second direction with an angle other than 90°.
6. The apparatus of claim 4 ,
wherein an upper surface of each of the first and second conductive trunk lines and the first and second conductive branch lines is lower than an upper surface of each of the first, second and third source/drain regions.