Integrated-circuitry overlay alignment mark, a substrate comprising an overlay alignment mark, a method of forming an overlay alignment mark in the fabrication of integrated circuitry, and a method of determining overlay alignment in the fabrication of integrated circuitry

1. A method of forming an overlay alignment mark in the fabrication of integrated circuitry, comprising:

forming a first series of first features on a substrate, the first features being periodically-horizontally-spaced relative to each other along a first horizontal direction, each of the first features extending along a second horizontal direction across a first horizontal area of the substrate and across a second horizontal area of the substrate that is adjacent to the first horizontal area of the substrate; and

forming a second series of second features above the first series of the first features, the second features being periodically-horizontally-spaced relative to each other along the first direction, a plurality of the second features each being directly above and covering at least a portion of one of the first features in the a first horizontal area of the substrate, an absence of the second features in the second horizontal area of the substrate, a first of the second features being connected to a second of the second features through an interconnect extending in the first direction within the first horizontal area.

2. The method of claim 1 wherein the first series of the first features are formed commonly within one level of the substrate and the second series of the second features are formed commonly within another level of the substrate that is above the one level.

3. The method of claim 1 wherein the first features and the second features have a one-to-one correspondence in the first horizontal area of the substrate.

4. The method of claim 1 wherein the first features and the second features do not have a one-to-one correspondence in the first area of the substrate.

5. The method of claim 1 comprising forming the second features to be continuous lines of a first material and forming the first features to be continuous lines of a second material.

6. The method of claim 5 wherein the first and second materials are both are conductive.

7. The method of claim 5 wherein one of the first material and the second material is conductive and the other is insulative.

8. The method of claim 5 comprising forming the second material into continuous lines of the individual second features by spacer patterning.

9. The method of claim 1 comprising forming the second features and the first features to be in respective straight lines.

10. The method of claim 9 comprising forming both of (a) the second features in their respective straight lines in the first horizontal area, and (b) the first features in their respective straight lines in both the first and second horizontal areas, to be continuous.

11. The method of claim 9 comprising forming at least one of (a) the second features in their respective straight lines, or (b) the first features in their respective straight lines, to be discontinuous.

12. The method of claim 11 comprising forming only one of (a) and (b) to be discontinuous.

13. The method of claim 11 comprising forming both of (a) and (b) to be discontinuous.

14. The method of claim 9 wherein the straight lines of the second features and number of the straight lines of the first features have a one-to-one correspondence.

15. The method of claim 9 wherein the straight lines of the second features and the straight lines of the first features do not have a one-to-one correspondence.

16. The method of claim 1 each of the first series of first features and second series of second features is horizontally elongated.

17. The method of claim 1 wherein the first and second horizontal areas are immediately-horizontally-adjacent one another.

18. The method of claim 1 wherein the second features are never directly above and never covering any portion of the first features in the second horizontal area.

19. The method of claim 1 comprising:

initially forming the second features to be directly above and covering at least some portion of the first features in the second horizontal area; and

after said initially forming, removing all of the individual second features in the second horizontal area.

20. The method of claim 1 wherein the substrate comprises a plurality of integrated-circuit dies having scribe-line area between immediately-adjacent of the dies, the overlay alignment mark being formed in the scribe-line area.

21. A method of forming an overlay alignment mark in the fabrication of integrated circuitry, comprising:

forming a first series of first features on a substrate, the first features being periodically-horizontally-spaced relative to each other along a first horizontal direction, each of the first features extending along a second horizontal direction across a first horizontal area of the substrate and across a second horizontal area of the substrate that is adjacent to the first horizontal area of the substrate;

forming a second series of second features above the first series of the first features, the second features being periodically-horizontally-spaced relative to each other along the first direction, a first plurality of the second features each being directly above and covering at least a portion of one of the first features in the a first horizontal area of the substrate, with the plurality multiple of the first features being present within the first horizontal area of the substrate, an absence of the second features in the second horizontal area of the substrate; and

forming a third horizontal area of the substrate that is spaced from the first horizontal area by the second horizontal area, wherein the first features comprised by the first series of first features extend across the third horizontal area of the substrate, and forming a second plurality of the second features directly above and covering at least a portion of the individual first features in the third horizontal area.

22. The method of claim 21 wherein,

the first and second horizontal areas are immediately-horizontally-adjacent one another; and

the second and third horizontal areas are immediately-horizontally-adjacent one another.

23. A method of determining overlay alignment in the fabrication of integrated circuitry, comprising:

forming a first series of first features on a substrate, the first features being periodically-horizontally-spaced along a first horizontal direction relative to each other; and

forming a second series second features directly above the first series of the first features, the second features being periodically-horizontally-spaced along the first horizontal direction relative to each other, each of the second features being directly above and covering at least a portion of one of the first features in a first horizontal area of the substrate that contains multiple of the first features, the second features not being directly above and not covering any portion of the first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area along a second horizontal direction, multiple of the first features being present in the second horizontal area;

forming an interconnect extending along the first direction within the first horizontal area, the interconnect connecting a first of the second features to a second of the second features; and

comparing horizontal alignment of the uncovered first features in the first horizontal area and the second features in the horizontally-adjacent second horizontal area relative to one another to determine overlay alignment of the second features relative to the first features.

24. An integrated-circuitry overlay alignment mark, comprising:

a first series of first features on a substrate, the first features being periodically-horizontally-spaced relative to each other along a first horizontal direction;

a second series of second features directly above the first series of the first features, the second features being periodically-horizontally-spaced relative to each other along the first horizontal direction, each of the second features being directly above and covering at least a portion of individual one of the first features in a first horizontal area of the substrate that encompasses multiple of the first features, the second features not being directly above and not covering any portion of any of the first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area along a second horizontal direction, multiple of the first features being present within the second horizontal area; and

an interconnect within the first horizontal area, the interconnect extending along the first direction and connecting a first of the second features to a second of the second features.

25. A substrate comprising:

a plurality of integrated-circuit dies having scribe-line area between immediately-adjacent of the dies; and

an overlay alignment mark in the scribe-line area, comprising:

a first series of first features, the first series progressing along a first horizontal direction; and

a second series of second features directly above the first series features, each of the second features being directly above and covering at least a portion of one of the first features in a first horizontal area that encompasses multiple of the first features, the upper second features being absent in a second horizontal area that is horizontally adjacent the first horizontal area along a second horizontal direction, multiple of the first features being present in the second horizontal direction; and

a third series of second features directly above the first series of first features, each of the second features in the third series being directly above and covering at least a portion of one of the first features in a third horizontal area that is spaced from the first horizontal area in the second direction, the second horizontal are being between the first horizontal are and the second horizontal area.