IP Library Granted Patent US 11,126,453
Granted Patent B2
US 11,126,453 · App. 16/295,708 · Granted Sep 21, 2021

Protected regions management of memory

Inventors: Brent Keeth (Boise, ID); Naveh Malihi (University City, MO)
Assignee: Micron Technology, Inc.
G06F9/45558G06F12/145H04L9/14G06F21/6245G06F2009/45562G06F2009/45575G06F2009/45583G06F2009/45587G06F2212/1052
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,126,453
App. No.
16/295,708
Granted
Sep 21, 2021
Kind
B2
Abstract

Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called “protected regions”). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.

Claims (24)

1. An apparatus, comprising:

a host configured to host a plurality of virtual machines (VMs) via a plurality of processors; and

a memory resource, comprising an array of memory cells, external to the host and coupled to the host, via a physical interface comprising a plurality of buses where the host and the memory resource are implemented on separate integrated circuits, and shared by the plurality of VMs;

wherein the memory resource comprises a plurality of regions each allocated to respective ones of the plurality of VMs and each having a respective key associated therewith, and wherein a respective address space of each region is unique relative to the other regions of the plurality of regions;

wherein the memory resource is configured to:

receive an access command from one of the plurality of VMs and a key associated with the received access command;

compare, at the memory resource, the key associated with the received access command to a key associated with one region of the plurality of regions by accessing a register of the memory resource that can be written to by the host but cannot be accessed by the host, wherein each of the plurality of VMs is uniquely associated with only the respective key associated with the one region of the plurality of regions;

allow access to the one region of the plurality based at least in part on determining that the key associated with the received access command matches the key associated with the one region of the plurality of regions by modifying a mode register corresponding to the one region from a locked mode to an unlocked mode; and

prevent access based at least in part on determining that the key associated with the received access command does not match the key associated with the one region of the plurality of regions.

2. The apparatus of claim 1 , wherein the host is further configured to host a hypervisor and wherein the hypervisor is configured to assign a plurality of keys corresponding to the plurality of regions to the plurality of VMs.

3. The apparatus of claim 2 , wherein the hypervisor is configured to assign the plurality of regions and the plurality of keys to the plurality of VMs at startup.

4. The apparatus of claim 2 , wherein the hypervisor is configured to assign the plurality of regions and the plurality of keys to the plurality of VMs responsive to a creation of the plurality of VMs.

5. The apparatus of claim 2 , wherein the hypervisor is configured to assign the plurality of regions and the plurality of keys to the plurality of VMs utilizing a command that initializes a security mode provided to the memory resource.

6. The apparatus of claim 1 , wherein the plurality of VMs are configured to generate and store a plurality of keys corresponding to the plurality of regions in the memory resource.

7. A method, comprising:

receiving, at a memory resource, an access command from one of a plurality of virtual machines (VMs) hosted by a host via a plurality of processors and a key associated with the received access command,

wherein the memory resource is shared by the plurality of VMs,

wherein the memory resource comprises a plurality of regions each allocated to respective ones of the plurality of VMs and each having a respective key associated therewith,

wherein a respective address space of each region is unique relative to the other regions of the plurality of regions,

wherein the memory resource comprises an array of memory cells and is external to and coupled to the host via a physical interface comprising a plurality of buses, and

wherein the host and the memory resource are implemented on separate integrated circuits;

comparing, at the memory resource, the key associated with the received access command to a key associated with one region of the plurality of regions by accessing a register of the memory resource that can be written to by the host but cannot be accessed by the host, wherein each of the plurality of VMs is uniquely associated with only the respective key associated with the one region of the plurality of;

allowing, at the memory resource, access to the one region of the plurality based at least in part on determining that the key associated with the received access command matches the key associated with the one region of the plurality of regions by modifying a mode register corresponding to the one region from a locked mode to an unlocked mode; and

preventing, at the memory resource, access based at least in part on determining that the key associated with the received access command does not match the key associated with the one region of the plurality of regions.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2019
From: KEETH, BRENT; MALIHI, NAVEH
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048533/0401 →