IP Library Granted Patent US 10,983,852
Granted Patent B2
US 10,983,852 · App. 16/262,111 · Granted Apr 20, 2021

Power management component for memory sub-system voltage regulation

Inventors: Michael R. Spica (Eagle, ID); Patrick T. Caraher (Niwot, CO)
Assignee: Micron Technology, Inc.
G06F11/0727G06F11/0751G06F11/3037G06F11/3058
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Quick Facts
Patent No.
US 10,983,852
App. No.
16/262,111
Granted
Apr 20, 2021
Kind
B2
Abstract

A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.

Claims (48)

1. A memory sub-system, comprising:

a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system;

wherein the power management component is configured to:

adjust, until an operation state change of a particular component is detected, a regulator voltage level to a number of different voltage levels such that a first threshold voltage level is compared to the number of different voltage levels, wherein the regulator voltage level is provided to the particular component;

adjust, subsequent to the detection of the operation state change, the first threshold voltage level to a second threshold voltage level;

adjust, until the operation state change of the particular component is detected, the regulator voltage level to the number of different voltage levels such that the second threshold voltage level is compared to the number of different voltage levels of the regulator output voltage; and

determine a value of the regulator voltage level at which the operation state change of the particular component is detected based on the first threshold voltage level and the second threshold voltage level.

2. The memory sub-system of claim 1 , wherein the operation state change of the particular component comprises a change from a first state to a brownout state.

3. The memory sub-system of claim 1 , wherein the power management component is configured to determine the value of the regulator voltage level at which the operation state change of the particular component is detected by using at least one of:

a comparator internal to the power management component, the comparator having a programmable threshold level; or

an analog to digital converter internal to the power management component.

4. The memory sub-system of claim 3 , wherein the power management component is further configured to determine the value of the regulator voltage level at which the operation state change of the particular component is detected by adjusting the programmable threshold level of the comparator in a number of particular increments.

5. The memory sub-system of claim 1 , wherein the power management component is configured to detect the operation state change by monitoring a state of a power status signal of the particular component.

6. The memory sub-system of claim 1 , wherein the power management component is configured to detect the operation state change by detecting a communication failure of the particular component.

7. The memory sub-system of claim 6 , wherein the power management component is coupled to a controller configured to control a number of memory components, wherein the particular component is one of the number of memory components, and wherein the controller is configured to detect the communication failure of the particular component.

8. The memory sub-system of claim 1 , wherein the power management component is further configured to determine an operating voltage range of the particular component based on the value of the regulator voltage level at which the operation state change of the particular component is detected.

9. The memory sub-system of claim 1 , wherein the power management component is further configured to determine the value of the regulator voltage level at which the operation state change of the particular component is detected without directly probing the regulator voltage level provided to the particular component via a test circuit external to the memory sub-system.

10. The memory sub-system of claim 1 , wherein the memory-subsystem comprises a solid state drive (SSD), and wherein the power management component comprises a power management integrated circuit (PMIC).

11. A method, comprising:

providing an operating voltage from a power management component of a memory sub-system to a particular component of the memory sub-system via a regulator of the power management component;

adjusting a voltage level of the operating voltage output by the regulator to a number of different voltage levels such that a first threshold voltage level is compared to the number of different voltage levels of the voltage level of the operating voltage;

adjusting, in response to detecting an occurrence of an operation state change of the particular component due to the adjusting of the voltage level, the first threshold voltage level to a second threshold voltage level;

adjusting, until the operation state change of the particular component is detected, the voltage level of the operating voltage to the number of different voltage levels such that the second threshold voltage level is compared to the number of different voltage levels of the voltage level of the operating voltage; and

determining the voltage level of the operating voltage at which the operation state change of the particular component is detected based on the first threshold voltage and the second threshold voltage.

12. The method of claim 11 , further comprising determining the voltage level of the operating voltage at which the operation state change of the particular component is detected via circuitry internal to the power management component.

13. The method of claim 11 , further comprising adjusting the voltage level of the operating voltage output by the regulator via pulse width modulation.

14. The method of claim 11 , wherein the operation state change comprises a change from a first state to a brown out state, and wherein the method includes adjusting the voltage level of the operating voltage output by the regulator until the particular component reaches the brown out state.

15. The method of claim 11 , wherein adjusting the voltage level of the operating voltage output by the regulator comprises:

decreasing the voltage level of the operating voltage output by the regulator from a first voltage level until a first operation state change is detected; and

increasing the voltage level of the operating voltage output by the regulator to a voltage level above the first voltage level until a second operation state change is detected.

16. The method of claim 11 , further comprising determining an operating voltage range for the particular component based on a voltage level of the operating voltage initially output by the regulator and the voltage level of the operating voltage at which the operation state change of the particular component is detected.

17. A power management component, comprising:

a plurality of regulators configured to supply respective operating voltages for components of a memory sub-system;

feedback circuitry coupled to the plurality of regulators and to a control component, the feedback circuitry configured to:

compare a voltage level of a regulator output voltage provided to a particular component with a first threshold voltage level; and

provide, to the control component, a feedback signal indicating a result of the comparison; and

wherein the control component is configured to:

adjust, until an operation state change of the particular component is detected, the voltage level of the regulator output voltage to a number of different voltage levels such that the first threshold voltage level is compared to the number of different voltage levels of the regulator output voltage;

adjust, subsequent to the detection of the operation state change, the first threshold voltage level to a second threshold voltage level;

adjust, until the operation state change of the particular component is detected, the voltage level of the regulator output voltage to the number of different voltage levels such that the second threshold voltage level is compared to the number of different voltage levels of the regulator output voltage; and

determine an operation voltage level at which the operation state change of the particular component is detected based on the first threshold voltage level and the second threshold voltage level.

18. The power management component of claim 17 , wherein the control component is configured to determine the operation voltage level using an interpolation based on the first threshold voltage level and the second threshold voltage level.

19. The power management component of claim 17 , wherein:

a first feedback signal indicating a result of the comparison between the first threshold voltage level and a particular one of the number of different voltage levels of the regulator output voltage comprises a signal having a first status; and

a second feedback signal indicating a result of the comparison between the second threshold voltage level and the particular one of the number of different voltage levels of the regulator output voltage comprises a signal having a second status.

20. The power management component of claim 19 , wherein:

the first status indicates that the first threshold voltage level is greater than the particular one of the number of different voltage levels of the regulator output voltage; and

the second status indicates that the second threshold voltage level is less than the particular one of the number of different voltage levels of the regulator output voltage.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2019
From: SPICA, MICHAEL R.; CARAHER, PATRICK T.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048213/0227 →