Apparatuses and methods for internal voltage generating circuits

1. An apparatus comprising:

a voltage generator circuit including:

a plurality of serially-coupled resistors disposed in a first region;

a plurality of selector switches disposed in the first region and each coupled to a respective node between a pair of the plurality of serially-coupled resistors, wherein each of the plurality of selector switches is configured to be selectively, activated to provide a respective voltage from the respective node, wherein the plurality of selector switches are surrounded by the plurality of resistors disposed in the first region; and

an amplifier coupled to the plurality of selector switches and configured to receive the respective voltage from the plurality of serially-coupled resistors.

2. The apparatus of claim 1 , wherein the amplifier is disposed in a second region different from the first region.

3. The apparatus of claim 1 , wherein the voltage generator circuit further comprises a wiring track, wherein the wiring track is configured to couple the plurality selector switches to the amplifier to provide the at least one voltage to an input of the amplifier.

4. An apparatus comprising:

a voltage generator circuit including:

a plurality of serially-coupled resistors disposed in a first region;

a plurality of selector switches disposed in the first region and each coupled to a respective node between a pair of the plurality of serially-coupled resistors, wherein each of the plurality of selector switches is configured to be selectively activated to provide a respective voltage from the respective node and wherein each of the plurality of selector switches includes a respective PMOS and NMOS transistor pair; and

an amplifier coupled to the plurality of selector switches and configured to receive the respective voltage from the plurality of serially-coupled resistors,

wherein a first and a second resistor of the plurality of serially coupled resistors are disposed between the respective PMOS and NMOS transistor pair of a respective one of the plurality of selector switches.

5. The apparatus of claim 4 , wherein a PMOS transistor of the respective PMOS and NMOS transistor pair of the respective one of the plurality of selector switches is positioned nearer to the amplifier than the NMOS transistor of the respective PMOS and NMOS transistor pair of the respective one of the plurality of selector switches.

6. The apparatus of claim 4 , wherein the plurality of resistors includes a group of resistors extending in a first direction in parallel with one another and are aligned with one other in a second direction perpendicular to the first direction.

7. The apparatus of claim 6 , wherein each resistor of the group of resistors includes a respective metal region configured to provide at least one pullout of at least one contact of a plurality of contacts disposed adjacent to the respective metal regions.

8. The apparatus of claim 7 , wherein the plurality of resistors are coupled to the plurality of selector switches using common layer metal.

9. A voltage generator circuit comprising:

a plurality of resistors;

an amplifier;

a wiring track coupled to the amplifier; and

a plurality of selector switches integrated with the plurality of resistors and coupled to the wiring track, wherein one of the plurality of selector switches is configured to be enabled to provide respective voltage to the amplifier via the wiring track while remaining selector switches of the plurality of selector switches remain disabled, wherein the plurality of resistors surround the plurality of selector switches.

10. A voltage generator circuit comprising:

a plurality of resistors;

an amplifier;

a wiring track coupled to the amplifier; and

a plurality of selector switches integrated with the plurality of resistors and coupled to the wiring track, wherein one of the plurality of selector switches is configured to be enabled to provide respective voltage to the amplifier via the wiring track while remaining selector switches of the plurality of selector switches remain disabled, wherein a group of resistors of the plurality of resistors are disposed between a respective PMOS and a respective NMOS transistor of a respective one of the plurality of selector switches.

11. The voltage generator circuit of claim 10 , wherein a respective first end of each the group of resistors is coupled to a respective first contact disposed adjacent to a corresponding first metal region and a respective second end of each the group of resistors is coupled to a respective second contact disposed adjacent to a corresponding second metal region.

12. The voltage generator circuit of claim 11 , wherein a segment of a metal layer is coupled to the respective one of the plurality of selector switches and extends vertically and overlaps each resistor of the group of resistors.

13. The voltage generator circuit of claim 10 , wherein a respective gate of the PMOS transistor and a respective gate of the NMOS transistor each have a U shape.

14. The voltage generator circuit of claim 13 , wherein the group of resistors includes at least three resistors.

15. The voltage generator circuit of claim 10 , wherein the plurality of resistors includes a group of resistors aligned with one other in a first direction.

16. The voltage generator circuit of claim 15 , wherein each of the group of resistors extending in a second direction in parallel, wherein the second direction is perpendicular to the first direction.

17. The voltage generator circuit of claim 15 , wherein each of the group of resistors have a U-shape oriented with sides of the U-shape extending in parallel in a second direction, wherein the second direction is perpendicular to the first direction.