Quadrature signal generation

1. An apparatus, comprising:

a quadrature signal generator configured to:

generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal; and

provide the plurality of quadrature clock signals to a memory system;

wherein:

the filter bank is one of a plurality of components included in the quadrature signal generator;

at least one of the plurality of components comprises a capacitor bank whose constituent capacitors are controllable by respective control bits.

2. The apparatus of claim 1 , wherein the differential signal is received from a clock generator coupled to the quadrature signal generator.

3. The quadrature signal generator of claim 2 , wherein the clock generator comprises a phase locked loop (PLL).

4. The apparatus of claim 1 , wherein the quadrature signal generator comprises a filter bank and is configured to use the filter bank to generate the plurality of quadrature clock signals.

5. A quadrature signal generator, comprising:

an input channel configured to receive a differential signal having a non-sinusoidal waveform from a clock generator, wherein the quadrature signal generator is configured to convert the received differential signal to a sinusoidal waveform; and

a polyphase filter configured to:

receive the differential signal having the converted sinusoidal waveform; and

generate a plurality of quadrature signals having the sinusoidal waveform.

6. The quadrature signal generator of claim 5 , wherein the quadrature signal generator is configured to:

convert the plurality of quadrature signals generated at the polyphase filter to the non-sinusoidal waveform; and

generate, based on the plurality of quadrature signals having the converted non-sinusoidal waveform, a plurality of quadrature clock signals having the non-sinusoidal waveform;

wherein the plurality of quadrature clock signals generated at the quadrature clock generator are used to control timing operations of a memory system.

7. The quadrature signal generator of claim 5 , wherein the polyphase filter comprises a plurality of filter input channels, and wherein:

at least a portion of the plurality of filter input channels is configured to receive the differential signal having the converted sinusoidal waveform; and

at least another portion of the plurality of filter input channels is configured to receive a DC bias voltage.

8. The quadrature signal generator of claim 5 , further comprising a duty cycle adjuster configured to adjust a duty cycle of the differential signal received from the clock generator.

9. The quadrature signal generator of claim 5 , further comprising a smoothing filter, and the quadrature signal generator is configured to use the smoothing filter to convert the waveform of the differential signal.

10. The quadrature signal generator of claim 5 , further comprising a limiting amplifier sub-block, and wherein the quadrature signal generator is configured to use the limiting amplifier sub-block to convert the plurality of quadrature signals generated at the polyphase filter to the non-sinusoidal waveform.

11. The quadrature signal generator of claim 5 , wherein the limiting amplifier sub-block comprises an offset adjuster configured to correct a duty cycle error of the plurality of quadrature signals generated at the polyphase filter.

12. The quadrature signal generator of claim 5 , further comprising a phase adjuster, and the quadrature signal generator is configured to correct, using the phase adjuster, a phase error between an in-phase (I) signal and a quadrature (Q) signal of the plurality of quadrature signals generated at the polyphase filter.

13. The quadrature signal generator of claim 5 , wherein the polyphase filter is a passive polyphase filter (PPF).

14. A method, comprising:

generating, at a polyphase filter of a quadrature signal generator, a plurality of quadrature signals having a sinusoidal waveform at a same frequency as that of a differential signal received from a clock generator;

converting, to a non-sinusoidal waveform, the plurality of quadrature signals generated at the polyphase filter; and

generating, based on the plurality of quadrature signals having the converted non-sinusoidal waveform, a plurality of quadrature clock signals having the non-sinusoidal waveform.

15. The method of claim 14 , further comprising:

receiving the differential signal having the non-sinusoidal waveform from the clock generator;

converting a waveform of the differential signal having the non-sinusoidal waveform to the sinusoidal waveform; and

providing, to the polyphase filter, the differential signal having the sinusoidal waveform such that the plurality of quadrature signals are generated based on the differential signal having the sinusoidal waveform.

16. The method of claim 14 , further comprising, prior to generating the plurality of quadrature signals, adjusting a duty cycle of the differential signal having the non-sinusoidal waveform.

17. The method of claim 14 , converting the waveform of the differential signal having the non-sinusoidal waveform to the sinusoidal waveform further comprises changing a slew rate of the plurality of quadrature signals generated at the polyphase filter until a waveform of the plurality of quadrature signals is converted to the non-sinusoidal waveform.

18. The method of claim 14 , further comprising correcting a phase error between an in-phase (I) signal and a quadrature (Q) signal of the plurality of quadrature signals generated at the polyphase filter.

19. The method of claim 14 , wherein the non-sinusoidal waveform is a square waveform, and wherein the method further comprises providing the plurality of quadrature clock signals to a memory system.