High-voltage shifter with reduced transistor degradation

1. A memory device, comprising:

a group of memory cells; and

a high-voltage shifter circuit, including:

a signal transfer circuit including a P-channel transistor coupled between an input port and an output port of the high-voltage shifter circuit, the P-channel transistor configured to transfer a high-voltage input received at the input port to an access line controllably coupled to one or more of the group of memory cells;

a first high-voltage control (HVC 1 ) circuit configured to controllably couple a bias voltage to the P-channel transistor for a first time period; and

a second high-voltage control (HVC 2 ) circuit configured to controllably couple a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to protect against degradation of the P-channel transistor.

2. The memory device of claim 1 , wherein the signal transfer circuit further includes an N-channel transistor having a gate coupled to the control signal, the N-channel transistor and the P-channel transistor serially connected and coupled between the input port and the output port of the high-voltage shifter circuit.

3. The memory device of claim 2 , wherein the P-channel transistor is a high-voltage PMOS transistor with a positive threshold voltage, and the N-channel transistor is a high-voltage NMOS transistor with a negative threshold voltage.

4. The memory device of claim 1 , wherein:

the HVC 1 circuit is configured to, at an end of the first time period, decouple the bias voltage from the P-channel transistor and couple a ground potential (Vss) to the P-channel transistor; and

the HVC 2 circuit is configured to, after a specified switching delay from the end of the first time period, couple the stress-relief signal to the P-channel transistor.

5. The memory device of claim 1 , wherein the HVC 1 circuit is configured to decouple the bias voltage from, and to couple to the ground potential (Vss) to, the P-channel transistor in response to an output voltage at the output port substantially reaching a value of the high-voltage input at the input port.

6. The memory device of claim 1 , wherein the HVC 1 circuit is coupled to a gate of a first N-channel transistor, the first N-channel transistor having a source connected to a gate of the P-channel transistor.

7. The memory device of claim 6 , wherein the bias voltage has a value substantially equal to a supply voltage (Vcc).

8. The memory device of claim 1 , further comprising a high-voltage support (HVS) circuit configured to generate the stress-relief signal, and to couple the stress-relief signal to a drain of a second N-channel transistor; and

wherein the HVC 2 circuit is coupled to a gate of the second N-channel transistor to control the transfer of the stress-relief signal to the gate of P-channel transistor.

9. The memory device of claim 8 , wherein the HVS circuit includes a multiplexer configured to switch between a high-voltage source and a ground potential (Vss).

10. The memory device of claim 8 , wherein the high-voltage source of the HVS circuit has a voltage proportional to the high-voltage input.

11. The memory device of claim 1 , wherein the HVC 1 circuit includes a multiplexer configured to switch between a first voltage source and a ground potential (Vss).

12. The memory device of claim 1 , wherein the HVC 2 circuit includes a multiplexer configured to switch between a second voltage source and a ground potential (Vss).

13. The memory device of claim 1 , wherein the access line is configured to connect to the output port of the high-voltage shifter circuit, and the signal transfer circuit is configured to charge the access line using the transferred high-voltage input.

14. The memory device of claim 1 , wherein the access line includes a word line or a global word line.

15. A method of addressing potential degradation of a P-channel transistor of a signal transfer circuit in a high-voltage shifter of a memory device comprising a group of memory cells, the method comprising, in response to a shifter enabling signal:

generating a first control signal using a first high-voltage control (HVC 1 ) circuit to controllably couple a bias voltage to the P-channel transistor for a first time period, and at an end of the first time period, to decouple the bias voltage from, and couple to a ground potential (Vss) to, the P-channel transistor;

generating a second control signal using a second high-voltage control (HVC 2 ) circuit to controllably couple a stress-relief signal to the P-channel transistor after a specified switching delay from the end of the first time period to protect the P-channel transistor against degradation; and

charging an access line, via the signal transfer circuit, by transferring a high-voltage input to the access line coupled to one or more of the group of memory cells.

16. The method of claim 15 , comprising monitoring an output voltage of the high-voltage shifter, and decoupling the P-channel transistor from the bias voltage and coupling to a ground potential (Vss) in response to the output voltage substantially reaching a value of the high-voltage input.

17. The method of claim 15 , comprising: generating the stress-relief signal using a high-voltage support (HVS) circuit; coupling the stress-relief signal to a drain of a second N-channel transistor; and coupling the HVC 2 circuit to a gate of the second N-channel transistor to controllably transfer the stress-relief signal to the gate of P-channel transistor.

18. The method of claim 15 , wherein the first control signal is substantially 5 Volts, the second control signal is substantially 20 Volts, and the stress relief signal is substantially 15 Volts.

19. The method of claim 15 , wherein the P-channel transistor is a high-voltage PMOS (HVP) transistor.

20. The method of claim 15 , wherein the access line includes a word line or a global word line, and the method comprises applying the transferred high-voltage input to program, erase, or read the one or more of the group of memory cells.