Memory device processing

1. An apparatus, comprising:

a memory device comprising a plurality of banks of memory cells, wherein particular banks of memory cells among the plurality of banks includes a bank processor configured to control memory operations for the bank on which the bank processor is located; and

a system processor resident on a bank of the memory device that does not include the bank processor, wherein the system processor is configured to control performance of memory operations for the memory device.

2. The apparatus of claim 1 , wherein the system processor is configured to cause performance of the memory operations without transferring a command to circuitry external to the memory device.

3. The apparatus of claim 1 , wherein the system processor comprises a reduced instruction set computing (RISC-V) processor having increased processing power in comparison to the bank processors on the particular banks.

4. The apparatus of claim 1 , wherein each bank among the plurality of banks includes a plurality of extended row address (XRA) components configured to operate as caches for the processor of each bank.

5. The apparatus of claim 1 , wherein the plurality of memory banks comprises a volatile memory device, and wherein the volatile memory device further includes an input/output interface to couple the volatile memory device to a non-volatile memory device.

6. The apparatus of claim 1 , wherein the memory device is DRAM device resident on a dual inline memory module (DIMM).

7. The apparatus of claim 1 , wherein the system processor is further configured to cause a processing-in-memory operation to be performed by at least one bank of the memory device.

8. The apparatus of claim 1 , wherein each bank among the plurality of banks includes:

a first extended row address (XRA) component configured to operate as at least one of an instruction cache for the system processor corresponding to the bank on which the system processor is deployed and as a data cache for the system processor corresponding to the bank on which the system processor is deployed;

a second XRA component configured to operate as a bank-to-bank transfer cache; and

a third XRA component configured to operate as a high-speed interface to store host instructions for the bank.

9. The apparatus of claim 1 , wherein the banks of memory cells further comprise sensing circuitry configured to perform logical operations on operands stored therein.

10. The apparatus of claim 9 , wherein the sensing circuitry is further configured to perform logical operations without sending or receiving a command from circuitry external to the memory device.

11. The apparatus of claim 1 , wherein the plurality of banks that includes the bank processor further include respective very long instruction word (VLIW) machines, and wherein the bank of the memory device that does not include the bank processor does not include a VLIW machine.

12. A method, comprising:

receiving, by a system processor resident on a particular memory bank on a memory device, instructions to orchestrate tasks performed by bank processors resident on banks of the memory device that are devoid of the system processor; and

executing, by the system processor, the instructions to orchestrate tasks performed by the bank processors.

13. The method of claim 12 , further comprising executing the instructions to perform the memory operation without sending or receiving commands from circuitry external to the memory device.

14. The method of claim 12 , wherein executing the instructions to orchestrate tasks performed by the bank processors further comprises executing the instructions to cause performance of a processing-in-memory operation using a memory bank that is devoid of the system processor.

15. The method of claim 12 , further comprising receiving, by the system processor, the instructions without enabling a double data rate interface of the memory device.

16. The method of claim 12 , wherein the memory device is DRAM device resident on a dual inline memory module (DIMM).