Dragging first pass read level thresholds based on changes in second pass read level thresholds

1. A system comprising:

a memory component; and

a processing device, operatively coupled to the memory component, to:

perform a first programming pass of a multi-pass programming operation on the memory component resulting in first pass programming distributions, wherein first read level thresholds are established between the first pass programming distributions;

perform a second programming pass of the multi-pass programming operation on the memory component resulting in second pass programming distributions;

perform a continuous read level calibration (cRLC) operation on the memory component to calibrate second read level thresholds between the second pass programming distributions; and

subsequent to performing the cRLC operation on the memory component to calibrate the second read level thresholds, adjust one or more of the first read level thresholds between the first pass programming distributions based on the second read level thresholds.

2. The system of claim 1 , wherein to perform the cRLC operation on the memory component to calibrate the second read level thresholds between the second pass programming distributions, the processing device is to:

adjust the second read level thresholds to a center value that results in a lowest bit error rate.

3. The system of claim 1 , the processing device is further to:

subsequent to performing the cRLC operation to calibrate the second read level thresholds between the second pass programming distributions, change one or more of the second read level thresholds between the second pass programming distributions;

wherein to adjust the one or more of the first read level thresholds between the first pass programming distributions based on the second read level thresholds, the processing device is further to:

determine the change in the one or more second read level thresholds; and

adjust the one or more of the first read level thresholds based on the determined change in the one or more second read level thresholds.

4. The system of claim 3 , wherein the one or more of the first read level thresholds are adjusted proportionally to the change in the one or more second read level thresholds.

5. The system of claim 3 , wherein to adjust the one or more of the first read level thresholds between the first pass programming distributions based on the second read level thresholds, the processing device is further to:

determine whether the change in the one or more second read level thresholds satisfies a rule, wherein the one or more of the first read level thresholds are adjusted responsive to determining that the change in the one or more second read level thresholds satisfies the rule.

6. The system of claim 1 , the processing device is further to:

program the memory component with default read level thresholds to establish the first read level thresholds between the first pass programming distributions.

7. The system of claim 1 , wherein a number of first pass programming distributions is less than or equal to a number of second pass programming distributions.

8. The system of claim 1 , wherein a cRLC operation on the memory component to calibrate the first read level thresholds is not performed between the performance of the first programming pass and the second programming pass of the multi-pass programming operation.

9. A system comprising:

a memory component; and

a processing device, operatively coupled to the memory component, to:

determine that read level thresholds between a first plurality of programming distributions associated with the memory component are calibrated;

subsequent to determining that the read level thresholds between the first plurality of programming distributions associated with the memory component are calibrated, change one or more of the read level thresholds between the first plurality of programming distributions; and

adjust one or more read level threshold between a second plurality of programming distributions based on the change to the one or more read level thresholds between the first plurality of programming distributions.

10. The system of claim 9 , wherein a number of the second plurality of programming distributions is less than or equal to the number of the first plurality of programming distributions.

11. The system of claim 9 , wherein to determine that the read level thresholds between the first plurality of programming distributions associated the memory component are calibrated, the processing device is to:

determine that the read level thresholds between the first plurality of programming distributions have been adjusted to a center value that results in a lowest bit error rate.

12. The system of claim 9 , wherein the one or more of read level thresholds between the second plurality of programming distributions are adjusted proportional to the change in the one or more read level thresholds between the first plurality of programming distributions.

13. The system of claim 9 , wherein to adjust the one or more read level thresholds between the second plurality of programming distributions based on the change to the one or more read level thresholds between the first plurality of programming distributions, the processing device is to:

determine whether the change in the one or more read level thresholds between the first plurality of programming distributions satisfies a rule, wherein the one or more of the read level thresholds between the second plurality of programming distributions are adjusted responsive to determining that the change in the one or more read level thresholds between the first plurality of programming distributions satisfies the rule.

14. A method comprising:

performing a first programming pass of a multi-pass programming operation on a memory component resulting in first pass programming distributions, wherein first read level thresholds are established between the first pass programming distributions;

performing a second programming pass of the multi-pass programming operation on the memory component resulting in second pass programming distributions;

performing a continuous read level calibration (cRLC) operation on the memory component to calibrate second read level thresholds between the second pass programming distributions; and

subsequent to performing the cRLC operation on the memory component to calibrate the second read level thresholds, adjusting, by a processing device, one or more of the first read level thresholds between the first pass programming distributions based on the second read level thresholds.

15. The method of claim 14 , wherein performing the cRLC operation on the memory component to calibrate the second read level thresholds between the second pass programming distributions, the method further comprising:

adjusting the second read level thresholds to a center value that results in a lowest bit error rate.

16. The method of claim 14 , further comprising

subsequent to performing the cRLC operation to calibrate the second read level thresholds between the second pass programming distributions, changing one or more of the second read level thresholds between the second pass programming distributions;

wherein adjusting the one or more of the first read level thresholds between the first pass programming distributions based on the second read level thresholds, the method further comprising:

determining the change in the one or more second read level thresholds; and

adjusting the one or more of the first read level thresholds based on the determined change in the one or more second read level thresholds.

17. The method of claim 16 , wherein the one or more of the first read level thresholds are adjusted proportionally to the change in the one or more second read level thresholds.

18. The method of claim 16 , wherein adjusting the one or more of the first read level thresholds between the first pass programming distributions based on the second read level thresholds, the method further comprising:

determining whether the change in the one or more second read level thresholds satisfies a rule, wherein the one or more of the first read level thresholds are adjusted responsive to determining that the change in the one or more second read level thresholds satisfies the rule.

19. The method of claim 14 , further comprising:

programming the memory component with default read level thresholds to establish the first read level thresholds between the first pass programming distributions.

20. The method of claim 14 , wherein a cRLC operation on the memory component to calibrate the first read level thresholds is not performed between the performance of the first programming pass and the second programming pass of the multi-pass programming operation.