IP Library Granted Patent US 10,622,056
Granted Patent B2
US 10,622,056 · App. 16/250,919 · Granted Apr 14, 2020

Apparatuses having compensator lines along wordlines and independently controlled relative to the wordlines

Inventors: Deepak Chandra Pandey (Boise, ID); Chandra Mouli (Boise, ID); Haitao Liu (Boise, ID)
Assignee: Micron Technology, Inc.
G11C11/4085G11C8/08G11C8/14H01L23/528H01L23/5329H01L23/53257H01L27/10805H01L27/10811H01L27/10823H01L27/10891
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Quick Facts
Patent No.
US 10,622,056
App. No.
16/250,919
Granted
Apr 14, 2020
Kind
B2
Abstract

Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

Claims (49)

1. An apparatus, comprising:

first and second trenches extending into a semiconductor material; the first and second trenches being lined with dielectric material;

a first transistor gate in the first lined trench, and a second transistor gate in the second lined trench; the first transistor gate being coupled with a first wordline, and the second transistor gate being coupled with a second wordline;

first, second and third source/drain regions within the semiconductor material; with the first transistor gate being between the first and second source/drain regions, and with the second transistor gate being between the second and third source/drain regions;

a first programmable structure coupled with the first source/drain region, and a second programmable structure coupled with the third source/drain region;

a bitline coupled with the second source/drain region;

a first compensator line within the first trench and extending along the first wordline, and spaced from the first wordline by a first dielectric region; the first compensator line not being electrically connected to the first wordline; and

a second compensator line within the second trench and extending along the second wordline, and spaced from the second wordline by a second dielectric region; the second compensator line not being electrically connected to the second wordline.

2. The apparatus of claim 1 wherein the first and second programmable structures are charge-storage devices.

3. The apparatus of claim 1 wherein the first and second programmable structures are capacitors.

4. The apparatus of claim 1 wherein:

the first source/drain region, second source/drain region and first transistor gate are together comprised by a first access transistor;

the second source/drain region, third source/drain region and second transistor gate are together comprised by a second access transistor;

the first wordline is operated at a first voltage while the first access transistor is in an OFF state, and the first compensator line is operated at a second voltage while the first wordline is operated at the first voltage; with the second voltage being greater than the first voltage; and

the second wordline is operated at the first voltage while the second access transistor is in an OFF state, and the second compensator line is operated at the second voltage while the second wordline is operated at the first voltage.

5. The apparatus of claim 4 wherein:

the first wordline is operated at a third voltage while the first access transistor is in an ON state, and the first compensator line is operated at the second voltage while the first wordline is operated at the third voltage; with the third voltage being greater than the second voltage; and

the second wordline is operated at the third voltage while the second access transistor is in an ON state, and the second compensator line is operated at the second voltage while the second wordline is operated at the third voltage.

6. The apparatus of claim 4 wherein:

the first wordline is operated at a third voltage while the first access transistor is in an ON state, and the first compensator line is operated at a fourth voltage while the first wordline is operated at the third voltage; with the third voltage not being greater than the fourth voltage; and

the second wordline is operated at the third voltage while the second access transistor is in an ON state, and the second compensator line is operated at the fourth voltage while the second wordline is operated at the third voltage.

7. An apparatus, comprising:

a trench extending into a semiconductor material;

a transistor gate in the trench and coupled with a wordline;

a driver coupled with the wordline;

first and second source/drain regions within the semiconductor material; with the transistor gate being between the first and second source/drain regions;

a bitline coupled with the second source/drain region;

a compensator line within the trench and extending along the wordline, and spaced from the wordline by a dielectric region; the compensator line being coupled to a controller and being controlled independently relative to the wordline.

8. The apparatus of claim 7 further comprising a programmable structure coupled with the first source/drain region.

9. The apparatus of claim 8 wherein the programmable structure is a charge-storage device.

10. The apparatus of claim 8 wherein the programmable structure is a capacitor.

11. The apparatus of claim 7 wherein:

the first source/drain region, second source/drain region and transistor gate are together comprised by an access transistor; and

the wordline is operated at a first voltage while the access transistor is in an OFF state, and the compensator line is operated at a second voltage while the wordline is operated at the first voltage; with the second voltage being greater than the first voltage.

12. The apparatus of claim 11 wherein:

the wordline is operated at a third voltage while the access transistor is in an ON state, and the compensator line is operated at the second voltage while the wordline is operated at the third voltage; with the third voltage being greater than the second voltage.

13. An apparatus, comprising:

a trench extending into a semiconductor material;

a stack of materials within the trench, the stack comprising a wordline, a dielectric material and a compensator line, the wordline being separated from the compensator line by the dielectric material;

a first source/drain region within the semiconductor material on a first side of the trench;

a second source/drain region within the semiconductor material on an opposing second side of the trench, the second source/drain region extending deeper into the semiconductor material than the first source/drain region;

a bitline coupled to the second source/drain region; and

a programmable structure coupled to the first source/drain region.

14. The apparatus of claim 13 wherein the wordline comprises a first conductive material comprising one or both of tungsten and ruthenium.

15. The apparatus of claim 14 wherein the compensator line comprises a second conductive material comprising one or both of tungsten and ruthenium.

16. The apparatus of claim 13 further comprising a driver coupled with the wordline and a controller coupled with the compensator line, wherein the compensator line is independently controlled relative to the wordline.

17. The apparatus of claim 16 wherein the compensator line is operated by the controller at a second voltage while the wordline is operated at a first voltage; the second voltage being greater than the first voltage.

18. The apparatus of claim 13 wherein the compensator line electrically floats.

19. The apparatus of claim 13 wherein the compensator line is coupled to an electrically grounded structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
Continuity (2)
Division 15633595 · Jun 26, 2017
Related Publication 20190172520A1 · Jun 6, 2019