IP Library Granted Patent US 10,546,639
Granted Patent B2
US 10,546,639 · App. 16/134,603 · Granted Jan 28, 2020

Multifunctional memory cells

Inventor: Arup Bhattacharyya (Essex Junction, VT)
Assignee: Micron Technology, Inc.
G11C14/0018H01L27/1157H01L27/11582G11C16/0466G11C16/10
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Quick Facts
Patent No.
US 10,546,639
App. No.
16/134,603
Granted
Jan 28, 2020
Kind
B2
Abstract

The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.

Claims (36)

1. A memory cell, comprising:

a gate element;

a charge transport element, wherein the charge transport element includes at least one of:

a nitride material

a silicon-rich nitride material; and

a hafnium oxynitride material;

a plurality of charge storage elements, wherein:

each respective charge storage element is configured to store a charge transported from the gate element and through the charge transport element to that respective charge storage element; and

each respective charge storage element includes a nitride material and a silicon-rich nitride material; and

a charge blocking element configured to prevent leakage of the charge stored by each respective charge storage element, wherein the charge blocking element includes:

a hafnium oxynitride material; and

a silicon dioxide material.

2. The memory cell of claim 1 , wherein the memory cell includes an additional charge storage element that includes a gallium nitride material.

3. The memory cell of claim 1 , wherein the plurality of charge storage elements includes volatile charge storage elements.

4. The memory cell of claim 1 , wherein the plurality of charge storage elements includes non-volatile charge storage elements.

5. The memory cell of claim 1 , wherein the memory cell includes a silicon substrate element adjacent the charge blocking element.

6. A memory cell, comprising:

a gate element;

a charge transport element, wherein the charge transport element includes:

a hafnium oxynitride material;

an oxide material; and

an oxygen-rich silicon oxynitride material or a silicon-rich nitride material; and

a plurality of charge storage elements, wherein:

each respective charge storage element is configured to store a charge transported from the gate element and through the charge transport element to that respective charge storage element; and

each respective charge storage element includes a nitride material and a silicon-rich nitride material.

7. The memory cell of claim 6 , wherein the charge transport element is adjacent the gate element.

8. The memory cell of claim 6 , wherein the gate element includes a tantalum nitride material.

9. The memory cell of claim 6 , wherein the nitride material of each respective charge storage element is a silicon oxynitride material.

10. A method of operating a memory cell, comprising:

transporting a charge from a gate element of the memory cell through a charge transport element of the memory cell having a hafnium oxynitride material and an oxide material to a charge storage element of the memory cell having a nitride material and a silicon-rich nitride material;

storing, by the charge storage element to which the charge is transported, the charge; and

preventing, by a charge blocking element of the memory cell, leakage of the charge stored by the charge storage element.

11. The method of claim 10 , wherein the method includes, subsequent to storing the charge by the charge storage element, transporting the charge from the charge storage element through the charge transport element to the gate element.

12. The method of claim 10 , wherein transporting the charge through the charge transport element includes tunneling an electron through the charge transport element.

13. The method of claim 10 , wherein the method includes transporting the charge during a program operation being performed on the memory cell.

14. The method of claim 10 , wherein the method includes transporting an additional charge from the gate element of the memory cell through the charge transport element of the memory cell to an additional charge storage element of the memory cell having a gallium nitride material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2018
From: BHATTACHARYYA, ARUP
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046903/0259 →
Continuity (2)
Continuation 15641736 · Jul 5, 2017
Related Publication 20190019552A1 · Jan 17, 2019