IP Library Granted Patent US 10,163,755
Granted Patent B2
US 10,163,755 · App. 15/498,321 · Granted Dec 25, 2018

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

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Quick Facts
Patent No.
US 10,163,755
App. No.
15/498,321
Granted
Dec 25, 2018
Kind
B2
Abstract

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Claims (15)

1. A method of packaging a semiconductor die assembly, comprising:

positioning at least a portion of a thermal transfer structure at a peripheral region of a first die, wherein a plurality of second dies are arranged in a stack and attached to the first die, wherein the peripheral region extends laterally outward from the stack of second dies, wherein the thermal transfer structure comprises a thermally conductive material including a sidewall, a top integrally formed with the sidewall, a cavity formed by the sidewall and the top, an inlet, and an outlet, and wherein

the inlet is a first passageway through a lower area of the sidewall and the outlet is a second passageway through an upper area of the sidewall;

the sidewall has a foundation configured to surround at least a portion of the first die and a shoulder configured to be positioned over the peripheral region of the first die; and

positioning the thermal transfer structure at the peripheral region of the first die comprises attaching the foundation to a package support substrate and attaching the shoulder to the peripheral region of the first die, wherein the stack of second dies is in the cavity; and

flowing an underfill material between the second dies after positioning the thermal transfer structure at the peripheral region of the first die, wherein the underfill material extends laterally from the stack of second dies, wherein the lateral extension of the underfill material is limited by the thermal transfer structure, and wherein flowing the underfill material between the second dies comprises injecting the underfill material into the cavity via the inlet.

2. The method of claim 1 wherein the method further comprises exhausting a portion of the underfill material from the cavity via the outlet and plugging the outlet.

3. The method of claim 1 wherein the inlet and the outlet are laterally offset from each other.

4. The method of claim 1 wherein the underfill material contacts sides of the second dies.

5. A method of packaging a semiconductor dies assembly, comprising:

positioning at least a portion of a thermal transfer structure at a peripheral region of a first die, wherein a plurality of second dies are arranged in a stack and attached to the first die, wherein the peripheral region extends laterally outward from the stack of second dies, wherein the thermal transfer structure comprises a thermally conductive material including a sidewall, a top integrally formed with the sidewall, a cavity formed by the sidewall and the top, an inlet, and an outlet, and wherein

the inlet and the outlet extend through the sidewall at substantially the same elevation;

the sidewall has a foundation configured to surround at least a portion of the first die and a shoulder configured to be positioned over the peripheral region of the first die; and

positioning the thermal transfer structure at the peripheral region of the first die comprises attaching the foundation to a package support substrate and attaching the shoulder to the peripheral region of the first die, wherein the stack of second dies is in the cavity; and

flowing an underfill material between the second dies after positioning the thermal transfer structure at the peripheral region of the first die, wherein the underfill material extends laterally from the stack of second dies, wherein the lateral extension of the underfill material is limited by the thermal transfer structure, and wherein flowing the underfill material between the second dies comprises injecting the underfill material into the cavity via the inlet.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2017
From: VADHAVKAR, SAMEER S.; LI, XIAO; GROOTHUIS, STEVEN K.; LI, JIAN; GANDHI, JASPREET S.; DERDERIAN, JAMES M.; HEMBREE, DAVID R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042156/0728 →