Refresh circuitry

1. An apparatus comprising:

a memory array comprising:

a main portion; and

a redundant portion; and

row hammer refresh circuitry configured to, responsive to a determination of a hammering event, occurring to a particular row in the redundant portion, refresh both the particular row and at least one adjacent row of the redundant portion at a different frequency than a frequency at which the main portion is refreshed.

2. The apparatus of claim 1 , wherein the determination of the hammering event includes a determination that a group of memory cells has been accessed at a threshold rate.

3. The apparatus of claim 1 , wherein the determination of the hammering event includes a determination that a group of memory cells has been accessed a threshold number of times within a refresh window.

4. The apparatus of claim 1 , wherein the redundant portion comprises at least two groups of memory cells coupled to different access lines.

5. The apparatus of claim 1 , wherein:

the hammering event is associated with a hammered access line coupling a group of memory cells in the redundant portion;

the hammered access line corresponds to a particular remapped access line of the main portion; and

at least one access line adjacent to the particular remapped access line is not refreshed responsive to the determination of the hammering event.

6. The apparatus of claim 1 , wherein the apparatus includes a controller coupled to the row hammer refresh circuitry and configured to determine hammering events.

7. An apparatus, comprising:

a memory array, wherein the memory array comprises:

a main portion; and

a redundant portion;

refresh circuitry coupled to the memory array to:

refresh at least a portion of the redundant portion in response to a determination of a hammering event occurring to a particular row in the redundant portion, wherein the refresh of the particular row and at least one adjacent row in the redundant portion is performed at a different frequency than a frequency at which the main portion is refreshed; and

refrain from refreshing a portion of the main portion in response to the determination of the hammering event; wherein the portion of the main portion is a first group of memory cells adjacent to a second group of memory cells of the main portion.

8. The apparatus of claim 7 , wherein a physical address of the second group of memory cells is mapped to the redundant portion.

9. The apparatus of claim 8 , wherein the at least a portion of the redundant portion is refreshed independent of which group of cells in the main portion the at least a portion is mapped to.

10. The apparatus of claim 7 , wherein the determined hammering event occurs on a group of cells coupled to an access line of the redundant portion.

11. The apparatus of claim 7 , comprising a controller configured to, responsive to an attempt to access the group of memory cells in the main portion whose physical address has been mapped to the redundant portion, access a portion of the redundant portion to which the physical address is mapped.

12. The apparatus of claim 11 , wherein the hammering event comprises the controller accessing the portion of the redundant portion greater than a threshold number of times in a particular amount of time.

13. A method, comprising:

accessing a first group of redundant memory cells of a memory array at a particular rate; and

refreshing, using hammer refresh circuitry, the first group of redundant memory cells and a second group of redundant memory cells in response to the first group being accessed at the particular rate, wherein the refreshing is performed on a time interval that is less than a system refresh of a main portion of memory cells.

14. The method of claim 13 , comprising refreshing main memory cells of the memory array at a rate different than the particular rate.

15. The method of claim 13 , wherein refreshing the first group and the second group of redundant memory cells comprises refreshing all redundant memory cells of the memory array.

16. The method of claim 13 , wherein the first group of redundant memory cells are accessed in response to a corresponding group of main memory cells determined to be defective.

17. The method of claim 13 , wherein the second group of redundant memory cells are refreshed independent of whether the second group of redundant memory cell and a group of memory cells adjacent to the second group of redundant memory cells are accessed.

18. The method of claim 13 , wherein refreshing the first group of redundant memory cells and the second group of redundant memory cells comprises refreshing the first and second groups of redundant memory cells by using counter circuitry to cycle through addresses associated with each of the rows of the redundant array.