IP Library Granted Patent US 10,489,079
Granted Patent B2
US 10,489,079 · App. 15/609,481 · Granted Nov 26, 2019

Memory system data management

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Quick Facts
Patent No.
US 10,489,079
App. No.
15/609,481
Granted
Nov 26, 2019
Kind
B2
Abstract

The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

Claims (32)

1. A method for managing data, comprising:

recording, by a buffer that is coupled to each of a plurality of memory devices, logical addresses for each portion of data received from a host by the buffer along with a data address indicating where each portion of the data is stored in the buffer;

receiving a notification from a memory device of the plurality of memory devices at the buffer, wherein the notification indicates that the memory device is ready to receive data from the buffer, and wherein the notification further indicates a next available address entry that includes a physical address of a next available location in the memory device;

locating a portion of the data in the buffer by matching the next available address entry in the notification with a next available data address entry in the buffer that includes the data address indicating where in the buffer the portion of the data is located;

receiving the located portion of the data at the memory device from the buffer in response to the ready status indicating that the memory is ready to receive the located portion of the data from the buffer; and

writing the located portion of the data to the next available location in the memory device.

2. The method of claim 1 , wherein the method includes determining the next available address entry based on a wear strategy implemented on the memory device.

3. The method of claim 1 , wherein the located portion of the data is allocated by the buffer in an order in which the notification was received by the buffer.

4. The method of claim 1 , wherein the method includes recording, in a transaction table, the logical address and a physical address of the located portion of the data written to the next available location in the memory device.

5. The method of claim 4 , wherein the method includes storing the transaction table in the buffer.

6. The method of claim 4 , wherein the method includes storing a copy of the transaction table in each of the memory devices.

7. A method for managing data, comprising:

recording, by a buffer that is coupled to each of a plurality of memory devices, logical addresses for each portion of data received from a host by the buffer along with a data address indicating where each portion of the data is stored in the buffer;

receiving a notification from a memory device of the plurality of memory devices at the buffer, wherein the notification indicates that the memory device is ready to receive data from the buffer, and wherein the notification further indicates a next available address entry that includes a physical address of a next available location in the memory device;

selecting a particular portion of the data in the buffer in response to matching the next available address entry in the notification with a next available data address entry in the buffer that includes the data address indicating where in the buffer the particular portion of the data is located;

sending the selected particular portion of the data from the buffer to the memory device; and

writing the selected particular portion of the data to the memory device in the next available location.

8. The method of claim 7 , further comprising the buffer allocating the particular portion of the data in an order in which the notification was received by the buffer.

9. The method of claim 7 , wherein the method includes performing an error correction (ECC) operation on the data prior to receiving the data from the host by the buffer.

10. The method of claim 9 , wherein the data is received from the host by the buffer in increments that are the size of a NAND page.

11. The method of claim 7 , wherein writing the selected particular portion of the data to the memory device includes writing the selected particular portion of the data in a NAND page increment.

12. An apparatus, comprising:

a plurality of memory devices coupled to a bus; and

a buffer coupled to the plurality of memory devices by the bus and configured to:

record logical addresses for each portion of data received from a host by the buffer along with a data address indicating where each portion of the data is stored in the buffer;

receive a notification from a memory device of the plurality of memory devices, wherein the notification indicates that the memory device is ready to receive data from the buffer, and wherein the notification further indicates a next available address entry that includes a physical address of a next available location in the memory device;

allocate a portion of the data in the buffer to the memory device in an order in which the notification is received by the buffer; and

locate the allocated portion of the data in the buffer by matching the next available address entry in the notification with a next available data address entry in the buffer that includes the data address indicating where in the buffer the allocated portion of the data is located.

13. The apparatus of claim 12 , wherein the buffer is configured to send the located allocated portion of the data from the buffer to the next available location in the memory device.

14. The apparatus of claim 13 , wherein the buffer is configured to store the logical address and a physical address of the allocated portion of the data sent to the memory device in a transaction table in the buffer.

15. The apparatus of claim 14 , wherein a copy of the transaction table is periodically stored in each memory device of the plurality of memory devices and the copy of the transaction table stored in each memory device is sent to the buffer upon powering up the apparatus.

16. The apparatus of claim 12 , wherein the buffer is configured to receive the data from a host and write the data in the buffer.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2017
From: GHODSI, RAMIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042542/0959 →