Clock signal and supply voltage variation tracking

1. An apparatus comprising:

a first tracking enablement circuit configured to enable a delay-locked loop tracking circuit based on a variation in a voltage output of a voltage source, a variation in a frequency of an input clock signal, or combinations thereof; and

a second tracking enablement circuit configured to enable a duty cycle correction circuit based on a variation in a duty cycle of the input clock signal.

2. The apparatus of claim 1 , wherein each of the first and second tracking enablement circuits comprises:

a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period based, at least in part, on the input clock signal;

a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first signal and the second signal; and

a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.

3. The apparatus of claim 1 ,

wherein the first tracking enablement circuit is further configured to disable the delay locked loop tracking circuit; and

wherein the second tracking enablement circuit is further configured to disable the duty cycle correction circuit.

4. An apparatus comprising:

a first circuit configured, when enabled, to perform a delay locked loop (DLL) operation;

a second circuit configured, when enabled, to perform a duty cycle correction (DCC) operation;

a first tracking enablement circuit configured to produce a first voltage based on a signal related to the DLL operation, the first tracking enablement circuit being further configured to enable the first circuit when a variation of the first voltage exceeds a first threshold value; and

a second tracking enablement circuit configured to produce a second voltage based on a signal related to the DCC operation, the second tracking enablement circuit being further configured to enable the second circuit when a variation of the second voltage exceeds a second threshold value.

5. The apparatus of claim 4 , wherein each of the first and second tracking enablement circuits comprises:

a clock generation circuit configured to generate a first signal and a second signal responsive to a corresponding one of the signal related to the DLL operation and the signal related to the DCC operation, the first signal and the second signal being non-overlapping, periodic signals;

a charge pump circuit coupled to the clock generation circuit and configured to generate a corresponding one of the first voltage and the second voltage responsive, at least in part, to the first signal and the second signal; and

a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare the corresponding one of the first voltage and the second voltage with a corresponding one of the first and second threshold values.

6. The apparatus of claim 5 , wherein each of the first voltage and the second voltage comprises a first sense voltage and a second sense voltage responsive, at least in part; to the first signal and the second signal, respectively; and wherein the comparison circuit is configured to compare a difference between the first sense voltage and the second sense voltage with the corresponding one of the first and second threshold values.

7. The apparatus of claim 6 , wherein the charge pump circuit comprises a first charging circuit and a second charging circuit.

8. The apparatus of claim 7 , wherein each of the first and second charging circuits comprises:

a pass gate configured to be coupled to a power supply voltage and further configured to allow current to flow from the power supply voltage based, at least in part, on a corresponding one of the first signal and the second signal; and

one or more capacitors configured to be charged in response to the pass gate allowing current to flow from the power supply voltage.

9. The apparatus of claim 8 , wherein the first sense voltage is generated by the first charging circuit and wherein the second sense voltage is generated by the second charging circuit.

10. The apparatus of claim 5 , wherein the clock generation circuit comprises a non-overlapping clock generator.

11. The apparatus of claim 10 , wherein the clock generation circuit comprises a frequency divider, the frequency divider being coupled to the non-overlapping clock generator.

12. The apparatus of claim 5 , wherein the comparison circuit represents at least one of static hysteresis and adaptive hysteresis.

13. A method comprising:

enabling, responsive to assertion of a first active signal, a first circuit to allow the first circuit to perform a delay locked loop (DLL) operation;

enabling, responsive to assertion of a second active signal, a second circuit to allow the second circuit to perform a duty cycle correction (DCC) operation;

producing a first voltage based on a signal related to the DLL operation;

producing a second voltage based on a signal related to the DCC operation;

asserting the first active signal when a variation of the first voltage exceeds a first threshold value; and

asserting the second active signal when a variation of the second voltage exceeds a second threshold value.

14. The method of claim 13 ,

wherein the producing the first voltage comprises:

generating a first signal and a second signal responsive to the signal related to the DLL operation, the first signal and the second signal being non-overlapping, periodic signals, and

generating the first voltage responsive, at least in part, to the first signal and the second signal; and

wherein the producing the second voltage comprises:

generating a third signal and a fourth signal responsive to the signal related to the DCC operation, the third signal and the fourth signal being non-overlapping, periodic signals, and

generating the second voltage responsive, at least in part, to the third signal and the fourth signal.

15. The method of claim 14 ,

wherein the generating the first voltage comprises generating a first sense voltage and a second sense voltage responsive, at least in part, to the first signal and the second signal, respectively; and

wherein the generating the second voltage comprises generating a third sense voltage and a fourth sense voltage responsive, at least in part, to the third signal and the fourth signal, respectively.

16. The method of claim 15 ,

wherein the asserting the first active signal comprises comparing a difference between the first sense voltage and the second sense voltage with the first threshold value; and

wherein the asserting the second active signal comprises comparing a difference between the third sense voltage and the fourth sense voltage with the second threshold value.