Apparatuses and methods for voltage buffering
An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer that includes two identical stages. The first stage is configured to receive an input voltage and produce an intermediate voltage as an output. The second stage is configured to receive the intermediate voltage and provide an output voltage that is equal to the input voltage. The voltage buffer may be coupled to a current source. The second stage of the voltage buffer may have current drive ability.
1. An apparatus comprising:
an input terminal configured to receive an input voltage;
an output terminal configured to provide an output voltage;
first and second voltage lines;
first and second nodes;
a current source coupled between the first voltage line and the first node;
a first transistor coupled between the first node and the second node, the first transistor including a gate coupled to the first node;
a second transistor coupled between the second node and the second voltage line, the second transistor including a gate coupled to the input terminal;
a third transistor coupled between the first node and the output terminal, the third transistor including a gate coupled to the first node; and
a fourth transistor coupled between the output terminal and the second voltage line, the fourth transistor including a gate coupled to the second node.
2. The apparatus of claim 1 , wherein each of the first, second, third and fourth transistors is of a first channel type.
3. The apparatus of claim 2 , wherein the first channel type is an n-channel type.
4. The apparatus of claim 2 , wherein the first, second, third and fourth transistors have identical transistor dimensions.
5. The apparatus of claim 2 , wherein the first, second, third and fourth transistors have identical transistor characteristics.
6. The apparatus of claim 2 , wherein the current source comprises a fifth transistor coupled between the first voltage line and the first node.
7. The apparatus of claim 6 , wherein the fifth transistor is of a second channel type.
8. The apparatus of claim 7 ; wherein the first channel type is an n-channel type and the second channel type is a p-channel type.
9. The apparatus of claim 1 , wherein the current source comprises a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are coupled to configure a current mirror.
10. The apparatus of claim 9 , wherein each of the first, second, third and fourth transistors is of a first channel type and each of the fifth and sixth transistors is of a second channel type.
11. The apparatus of claim 10 , wherein the first channel type is an n-channel type and the second channel type is a p-channel type.
12. An apparatus comprising:
a current source; and
a voltage buffer coupled to the current source;
wherein the voltage buffer is configured to receive an input voltage and provide an output voltage that is substantially equal to the input voltage;
wherein the voltage buffer comprises a first stage and a second stage coupled to the first stage; the first stage being configured to receive the input voltage and the second stage being configured to provide the output voltage;
wherein the first stage comprises a first node, a second node, a third node, a first transistor coupled between the first node and the second node, and a second transistor coupled between the second node and the third node; and
wherein the second stage comprises a fourth node, a fifth node, a sixth node, a third transistor coupled between the fourth node and the fifth node, and a fourth transistor coupled between the fifth node and the sixth node.
13. The apparatus of claim 12 , wherein the second transistor is configured to receive the input voltage, and the fourth transistor is configured to receive an intermediate voltage from the second node and provide the output voltage to the fifth node.
14. The apparatus of claim 13 , wherein each of the first transistor and the third transistor is coupled to configure a load.
15. The apparatus of claim 14 , wherein each of the first transistor and the third transistor includes a gate and a drain coupled to each other.
16. The apparatus of claim 12 , wherein the first node and the fourth node are coupled to the current source, and the third node and the sixth node are coupled to a reference voltage line.
17. The apparatus of claim 16 , wherein each of the first, second, third and fourth transistors is of a first channel type.
18. The apparatus of claim 17 , wherein the first channel type is an n-channel type.
19. The apparatus of claim 16 , wherein the current source comprises a fifth transistor coupled to the first node and the fourth node.
20. The apparatus of claim 19 , wherein each of the first, second, third and fourth transistors is of an n-channel type and the fifth transistor is of a p-channel type.