IP Library Granted Patent US 10,153,194
Granted Patent B2
US 10,153,194 · App. 15/584,413 · Granted Dec 11, 2018

Array of gated devices and methods of forming an array of gated devices

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Quick Facts
Patent No.
US 10,153,194
App. No.
15/584,413
Granted
Dec 11, 2018
Kind
B2
Abstract

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

Claims (12)

1. A method of forming an array of gated devices, the gated devices being arranged in rows and columns and comprising an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region, individual of the inner regions comprising a pillar that is spaced from the pillars of other inner regions in a horizontal cross section, the method comprising:

forming placeholder material-lines within bottoms of trenches between walls that longitudinally extend along one of rows or columns;

patterning the walls along the other of the rows or columns to form spaced pillars to individually comprise the inner region, the mid region, and the outer region of individual of the gated devices;

after the patterning, removing the placeholder material-lines to expose sidewalls of the inner regions of the pillars along the one of the rows or columns;

after the removing, depositing metal to be circumferentially surrounding, directly against, and electrically coupled to the sidewalls of the inner regions of the pillars;

forming a plurality of access lines elevationally outward of the metal and that individually are laterally proximate the mid regions along individual of the rows;

forming a plurality of data/sense lines that individually are elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns; and

the metal being electrically isolated from the data/sense lines.

2. The method of claim 1 wherein the inner regions are electrically coupled to one another elevationally inward of the metal, thereby being electrically coupled to one another by other than, and/or not solely by, the metal that is directly against the sidewalls of the inner regions of the pillars.

3. The method of claim 1 wherein the placeholder lines are formed to individually have a longitudinally extending void space therein.

4. The method of claim 1 comprising widening the bottoms of the trenches in comparison to elevationally outermost portions thereof prior to forming the placeholder lines.

5. The method of claim 1 wherein the walls and the placeholder lines longitudinally extend along the columns.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →