Apparatuses and methods for detecting frequency ranges corresponding to signal delays of conductive VIAS
View Patent ↗Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
1. An apparatus comprising:
a first semiconductor die configured to provide a first clock signal;
a first through-silicon via (TSV) configured to transfer the first clock signal therethrough to provide a second clock signal; and
a second semiconductor die configured to receive the second clock signal, the second semiconductor die comprising first circuitry configured to compare a phase of the second clock signal and a phase of a third clock signal related to the first clock signal.
2. The apparatus of claim 1 ,
wherein the second semiconductor die is further configured to provide a source clock signal, and
wherein the apparatus further comprises a second TSV configured to transfer the source clock signal from the second semiconductor die to the first semiconductor die as the first clock signal.
3. The apparatus of claim 2 , wherein the second semiconductor die further comprises second circuitry configured to provide the third clock signal responsive to the source clock signal.
4. The apparatus of claim 3 , wherein each TSV of the first and second TSVs penetrates through the second semiconductor die.
5. The apparatus of claim 1 ,
wherein the first semiconductor die further comprises second circuitry configured to provide the third clock signal, and
wherein the apparatus further comprises a second TSV configured to transfer the third clock signal to the second semiconductor die.
6. The apparatus of claim 5 , wherein each TSV of the first and second TSVs penetrates through the first semiconductor die.
7. An apparatus comprising a plurality of semiconductor dies stacked to each other, at least first and second semiconductor dies of the plurality of semiconductor dies being interconnected to each other by a through-silicon via (TSV),
wherein the first semiconductor die comprises an evaluation circuit configured to receive a clock signal from the TSV and further configured to generate an evaluation signal based on a transition of the clock signal dependent on effective capacitance of the TSV.
8. The apparatus of claim 7 , wherein the evaluation signal is indicative of a frequency range of the clock signal.
9. The apparatus of claim 7 , further comprising:
a delay circuit configured to model the effective capacitance of the TSV.
10. The apparatus of claim 7 ,
wherein the first semiconductor die is configured to receive a source clock signal from an outside of the first semiconductor die, and
wherein the evaluation circuit is configured to receive a divided clock signal of the source clock signal as the clock signal.
11. The apparatus of claim 7 , wherein the first semiconductor die is configured to receive the clock signal from the second semiconductor die through the TSV in the second semiconductor die.
12. The apparatus of claim 7 , wherein the first semiconductor die further comprises a time adjustment circuit configured to provide an adjusted clock signal responsive to the evaluation signal.
13. The apparatus of claim 7 , wherein the first semiconductor die further comprises a variable data transfer rate circuit configured to transfer a data responsive to the evaluation signal.
14. The apparatus of claim 7 , further comprising:
a controller configured to receive the evaluation signal and further configured to provide a timing training request to the first semiconductor die responsive to the evaluation signal.
15. The apparatus of claim 14 , wherein the second semiconductor die is configured to receive the timing training request from the first semiconductor die.
16. The apparatus of claim 7 ,
wherein the clock signal is a first clock signal, and
wherein the first semiconductor die is configured to receive a source clock signal from an outside of the first semiconductor die, to provide the source clock signal as a second clock signal to the outside of the first semiconductor die, and further configured to receive the second clock signal as the first clock signal through the TSV.
17. The apparatus of claim 8 , wherein the frequency range has two statuses.
18. The apparatus of claim 8 , wherein the frequency range has three or more statuses.
19. The apparatus of claim 8 , wherein the first semiconductor die comprises a second TSV configured to receive and provide the source clock signal.
20. The apparatus of claim 19 ,
wherein the second semiconductor die is configured to receive the second clock signal and further configured to provide the second clock signal.
21. A method comprising:
receiving a clock signal at a first end of a through silicon via (TSV) provided in a first semiconductor die;
providing the clock signal from a second end of the TSV; and
providing an evaluation signal based on a transition of the clock signal dependent on effective capacitance of the TSV.
22. The method of claim 21 , wherein the evaluation signal is provided at the first semiconductor die.
23. The method of claim 21 , wherein the evaluation signal is provided at a second semiconductor die stacked to the first semiconductor die.
24. The method of claim 21 , further comprising:
performing a timing training to transfer a data responsive to the evaluation signal.
25. The method of claim 21 , wherein the clock signal is a divided clock signal, the method further comprising:
receiving a source dock signal at the first semiconductor die; and
converting the source clock signal to the divided clock signal.
26. The method of claim 21 , further comprising:
receiving a source clock signal at the first semiconductor die; and
adjusting the source dock signal responsive to the evaluation signal.