Apparatuses and methods for shifting data
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.
1. An apparatus, comprising:
a first pre-charge line;
a second pre-charge line;
a first transistor including a gate coupled to the first pre-charge line, and a first terminal coupled to a first sense line and a second terminal coupled to a first voltage supply node;
a second transistor including a gate coupled to a first control line and a terminal coupled to the first sense line;
a first inverter including an input coupled to the first sense line;
a third transistor including a gate coupled to the second pre-charge line, and a first terminal coupled to a second sense line and a second terminal coupled to a second voltage supply node;
a fourth transistor including a gate coupled to a second control line, a first terminal coupled to an output of the first inverter, and a second terminal coupled to the second sense line; and
a second inverter including an input coupled to the second sense line.
2. The apparatus of claim 1 , wherein the apparatus is a shift register.
3. The apparatus of claim 1 , wherein the first sense line is coupled to a first memory cell and is on pitch therewith, and
wherein the second sense line is coupled to a second memory cell and is on pitch therewith.
4. The apparatus of claim 1 , wherein the first transistor, the second transistor, the first inverter, the third transistor, the fourth transistor, and the second inverter collectively comprise a compute component,
wherein the compute component is on pitch with the first sense line and the second sense line, and
wherein the apparatus includes a plurality of compute components.
5. The apparatus of claim 1 , further comprising:
a fifth transistor including a gate coupled to a third control line, a first terminal coupled to the first sense line, and a second terminal coupled to an output of the second inverter; and
a sixth transistor including a gate coupled to a fourth control line and a terminal coupled to the second sense line.
6. The apparatus of claim 5 , wherein the first transistor, the second transistor, the first inverter, the third transistor, the fourth transistor, the second inverter, the fifth transistor, and the sixth transistor collectively comprise a compute component,
wherein the compute component is on pitch with the first sense line and the second sense line; and
wherein the apparatus includes a plurality of compute components.
7. An apparatus, comprising:
an array comprising a plurality of columns of memory cells; and
a controller coupled to the array and configured to shift data, wherein, in order to shift the data, the controller is configured to cause:
pre-charging of a first node of a compute component coupled to a column of memory cells with an operating voltage; and
pre-charging of a second node of the compute component with the operating voltage.
8. The apparatus of claim 7 , wherein the apparatus further comprises:
a first pre-charge line; and
a second pre-charge line,
wherein the compute component comprises:
a first transistor coupled to the first pre-charge line and the first node; and
a second transistor coupled to the second pre-charge line and the second node, and wherein, in order to shift the data, the controller is further configured to:
enable the first pre-charge line to pass the operating voltage to the first node; and
enable the second pre-charge line to pass the operating voltage to the second node.
9. The apparatus of claim 8 , wherein, in order to shift the data, the controller is further configured to cause:
pre-charging of the first node prior to enabling a first signal control line; and
pre-charging of the second node prior to enabling a second signal control line.
10. The apparatus of claim 8 , wherein the compute component is a first compute component coupled to a first column of memory cells,
wherein the apparatus further comprises a third transistor coupled to the first node of the first compute component, a node of a second compute component coupled to a second column of memory cells, and a third signal control line;
wherein the first compute component and the second compute component are separated by at least one additional compute component; and
wherein the controller is further configured to cause pre-charging of the first node of the first compute component prior to enabling the third signal control line.
11. The apparatus of claim 8 , wherein the compute component is a first compute component coupled to a first column of memory cells,
wherein the apparatus further comprises a third transistor coupled to the second node of the compute component, a node of a second compute component coupled to a second column of memory cells, and a third signal control line;
wherein the first compute component and the second compute component are separated by at least one additional compute component; and
wherein the controller is further configured to cause pre-charging of the first node of the first compute component prior to enabling the third signal control line.
12. The apparatus of claim 8 , wherein the compute component further comprises:
a third transistor coupled to the first node; and
a fourth transistor coupled to the second node,
wherein the third transistor and the fourth transistor are configured to pass a low voltage relative to the operating voltage.
13. The apparatus of claim 7 , wherein the apparatus further comprises:
a sense amplifier coupled to the compute component and the column of memory cells; and
a logical operation selection logic coupled to the sense amplifier.
14. The apparatus of claim 13 , wherein the controller is further configured to cause logical operations to be performed, in parallel, using data values stored in the plurality of columns of memory cells.
15. The apparatus of claim 14 , wherein the controller is further configured to cause logical operations to be performed without transferring data via a bus.
16. A method for shifting data, comprising:
applying a first signal to a first pre-charge line that is coupled to a gate of a first transistor;
applying a second signal to a first control line that is coupled to a gate of a second transistor;
applying a third signal to a second pre-charge line that is coupled to a gate of a fourth transistor; and
applying a fourth signal to a second control line that is coupled to a gate of a fifth transistor.
17. The method of claim 16 , wherein the method includes applying a fifth signal to a third control line that is coupled to a gate of a sixth transistor.
18. The method of claim 16 , wherein the method includes:
applying a fifth signal to a third control line that is coupled to a gate of a sixth transistor; and
applying a sixth signal to a fourth control line that is coupled to a gate of a seventh transistor.
19. The method of claim 18 , wherein the method includes applying a seventh signal to a fifth control line that is coupled to a gate of an eighth transistor.
20. The method of claim 16 , wherein the method includes shifting a data value resulting from a logical operation.