Methods of operating memory under erase conditions

1. A method of operating a memory, comprising:

applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and

applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.

2. The method of claim 1 , wherein applying the first voltage level to the first semiconductor material electrically connected to the second semiconductor material through the first conductive material of the second conductivity type different than the first conductivity type comprises the first conductive material having a conductivity type opposite of the first conductivity type.

3. The method of claim 1 , wherein a difference between the second voltage level and the third voltage level is equal to an expected difference between the first voltage level and a voltage level of the second semiconductor material applied in response to applying the first voltage level to the first semiconductor material.

4. The method of claim 1 , wherein applying the first voltage level to the first semiconductor material electrically connected to the second semiconductor material through the first conductive material of the second conductivity type different than the first conductivity type comprises the first semiconductor material having a P-type conductivity and the first conductive material having an N-type conductivity.

5. The method of claim 1 , further comprising:

applying a fourth voltage level, less than the first voltage level, to a third semiconductor material of the first conductivity type electrically connected to the second semiconductor material through a second conductive material of the second conductivity type, and applying a fifth voltage level, less than the third voltage level, to a control gate of a further memory cell of the string of series-connected memory cells while applying the first voltage level to the first semiconductor material, applying the second voltage level to the control gate of the memory cell and applying the third voltage level to the control gate of the different memory cell;

wherein the third semiconductor material forms a channel region for the further memory cell.

6. The method of claim 5 , wherein the fourth voltage level is less than a voltage level applied to the second semiconductor material in response to applying the first voltage level to the first semiconductor material and applying the fourth voltage level to the third semiconductor material.

7. The method of claim 1 , further comprising:

applying the first voltage level to a third semiconductor material of the first conductivity type electrically connected to the second semiconductor material through a second conductive material of the second conductivity type, and applying the second voltage level to a control gate of a further memory cell of the string of series-connected memory cells while applying the first voltage level to the first semiconductor material, applying the second voltage level to the control gate of the memory cell and applying the third voltage level to the control gate of the different memory cell;

wherein the third semiconductor material forms a channel region for the further memory cell.

8. A method of operating a memory, comprising:

developing a voltage drop between a first channel region of a string of series-connected memory cells and a second channel region of the string of series-connected memory cells across a diode between the first channel region and the second channel region;

applying a first voltage level to a control gate of a memory cell of the string of series-connected memory cells formed around the first channel region; and

applying a second voltage level, different than the first voltage level, to a control gate of a different memory cell of the string of series-connected memory cells formed around the second channel region;

wherein a difference between the first voltage level and the second voltage level is determined in response to an expected value of the voltage drop developed between the first channel region and the second channel region.

9. The method of claim 8 , further comprising:

developing a voltage drop between the second channel region of the string of series-connected memory cells and a third channel region of the string of series-connected memory cells across a second diode between the second channel region and the third channel region;

applying a third voltage level to a control gate of a further memory cell of the string of series-connected memory cells formed around the third channel region.

10. The method of claim 9 , wherein the third voltage level is different than the second voltage level, and wherein a difference between the second voltage level and the third voltage level is determined in response to an expected value of the voltage drop developed between the second channel region and the third channel region.

11. The method of claim 10 , wherein the third voltage level is equal to the first voltage level.

12. The method of claim 10 , wherein the first voltage is greater than the second voltage level, and wherein the second voltage level is greater than the third voltage level.

13. The method of claim 10 , wherein the first voltage is less than the second voltage level, and wherein the second voltage level is less than the third voltage level.

14. A method of operating a memory, comprising:

applying a first voltage level to a first semiconductor material of a first conductivity type, wherein the first semiconductor material is electrically connected to a first conductive material of a second conductivity type different than the first conductivity type, wherein the first conductive material is electrically connected to a second conductive material of the second conductivity type through a second semiconductor material of the first conductivity type, wherein the second semiconductor material is electrically connected to a third semiconductor material of the first conductivity type through the second conductive material, wherein the first semiconductor material forms a channel region for a memory cell of a first portion of a string of series-connected memory cells, wherein the second semiconductor material forms a channel region for a memory cell of a second portion of the string of series-connected memory cells, and wherein the third semiconductor material forms a channel region for a memory cell of a third portion of the string of series-connected memory cells; and

applying a second voltage level to the third semiconductor material, applying a third voltage level less than the first voltage level to a control gate of the memory cell of the first portion of the string of series-connected memory cells, and applying a fourth voltage level less than the second voltage level to a control gate of the memory cell of the second portion of the string of series-connected memory cells while applying the first voltage level to the first semiconductor material;

wherein, when the first voltage level is less than the second voltage level, the third voltage level is less than the fourth voltage level; and

wherein, when the first voltage level is greater than or equal to the second voltage level, the third voltage level is greater than the fourth voltage level.

15. The method of claim 14 , wherein applying the first voltage level to the first semiconductor material comprises applying the first voltage level to the first semiconductor material through a third conductive material.

16. The method of claim 15 , wherein applying the first voltage level to the first semiconductor material through the third conductive material comprises applying the first voltage level to the first semiconductor material through the third conductive material electrically connected to a data line of the memory.

17. The method of claim 16 , further comprising:

applying a fifth voltage level to a control gate of the memory cell of the third portion of the string of series-connected memory cells while applying the first voltage level to the first semiconductor material, applying the second voltage level to the third semiconductor material, applying the third voltage level to the control gate of the memory cell of the first portion of the string of series-connected memory cells, and applying the fourth voltage level to the control gate of the memory cell of the second portion of the string of series-connected memory cells;

wherein the third voltage level and the fifth voltage level are each greater than the fourth voltage level.

18. The method of claim 16 , wherein applying the first voltage level to the first semiconductor material through the third conductive material comprises applying a fifth voltage level greater than the first voltage level to a fourth semiconductor material of the first conductivity type electrically connected to the first semiconductor material through the third conductive material.

19. The method of claim 16 , wherein applying the second voltage level to the third semiconductor material comprises applying the second voltage level to the third semiconductor material electrically connected to a source of the memory.

20. The method of claim 14 , wherein applying the second voltage level to the third semiconductor material comprises applying the second voltage level to the third semiconductor material through a third conductive material of the second conductivity type.