Method and apparatus for controlling access to a common bus by multiple components
Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.
1. An apparatus comprising:
a first memory die;
a first bus;
a common bus; and
an interface control logic stacked with the first memory die and coupled to the first memory die through the first bus and the common bus, the interface control logic including:
a plurality of delay circuits configured to output a plurality of strobe signals having different amounts of delay from one another; and
a multiplexer configured to select a first one of the plurality of strobe signals, responsive to a first command, based on a type of the first command and a first latency of the first memory die, transferred through the common bus and output the first one of the plurality of strobe signals to the first bus;
wherein the first memory die is configured to capture the first command responsive to the first one of the plurality of strobe signals.
2. The apparatus of claim 1 , wherein each of the plurality of delay circuits is a variable delay circuit and an amount of delay of each of the plurality of delay circuits is set in a training operation.
3. The apparatus of claim 1 , wherein the multiplexer is further configured to select a second one of the plurality of strobe signals, responsive to a second command, based on a type of the second command and the first latency of the first memory die, transferred through the common bus and output the second one of the plurality of strobe signals to the first bus, wherein the second command indicates a different operation from the first command; and
wherein the first memory die is further configured to capture the second command responsive to the second one of the plurality of strobe signals.
4. The apparatus of claim 3 , the first one of the plurality of strobe signals and the second one of the plurality of strobe signals are different in activated period of time from each other.
5. The apparatus of claim 4 , wherein the type of the first command is one of read and write commands, and wherein the type of the second command is the other of read and write commands.
6. The apparatus of claim 1 , further comprising:
a second memory die stacked with the first memory die, wherein the first memory die is stacked between the interface control logic and the second memory die; and
a second bus electrically independent of the first memory bus;
wherein the interface control logic is coupled to the second memory die through the second bus and the common bus and the multiplexer of the interface control logic is further configured to select a second one of the plurality of strobe signals, responsive to a second command, based on a type of the second command and a second latency of the second memory die, transferred through the common bus and output the second one of the plurality of strobe signals to the second bus; and
wherein the second memory die is configured to capture the second command responsive to the second strobe signal.
7. The apparatus of claim 6 , the first one of the plurality of strobe signals and the second one of the plurality of strobe signals are different in activated period of time from each other.
8. The apparatus of claim 7 , wherein the first command is a read command and the second command is a write command.
9. The apparatus of claim 7 , each of the first command and the second command is one of read and write commands.
10. An apparatus comprising:
an interface control logic;
a first memory die;
a second memory die;
a common bus coupled in common to the interface control logic, the first memo die and the second memory die;
a first bus coupled between the interface control logic and the first memory die and decoupled from the second memory die; and
a second bus coupled between the interface control logic and the second memory die and decoupled from the first memory die;
wherein the interface control logic, the first memory die and the second memory die are stacked on one another;
wherein the interface control logic is configured to transfer a first command, based on a first latency of the first memory die, through the common bus with providing a first strobe signal to the first bus, and wherein the interface control logic is further configured to transfer a second command, based on a second latency of the second memory die, through the common bus with providing a second strobe signal to the second bus; and
wherein the first memory die is configured to capture the first command responsive to the first strobe signal and the second memory die is configured to capture the second command responsive to the second strobe signal.
11. The apparatus of claim 10 , wherein the first strobe signal and the second strobe signal are different in activated period of time from each other.
12. The apparatus of claim 11 , wherein the type of the first command is one of read and write commands, and wherein the type of the second command is the other of read and write commands.
13. The apparatus of claim 11 , wherein each of the first command and the second command is one of read and write commands.
14. The apparatus of claim 10 , wherein a part of an activated period of time of the first strobe signal overlaps a part of an activated period of time of the second strobe signal.
15. The apparatus of claim 10 , wherein the interface control logic includes: a plurality of delay circuits configured to output a plurality of strobe signals having different amounts of delay from one another; and
a multiplexer configured to select a first one of the plurality of strobe signals as the first strobe signal responsive to the first command and select a second one of the plurality of strobe signals as the second strobe signal.
16. The apparatus of claim 15 , wherein each of the plurality of delay circuits is a variable delay circuit and an amount of delay of each of the plurality of delay circuits is set in a training operation.
17. The apparatus of claim 15 , wherein the first command is one of read and write commands and the second command is the other of read and write commands.
18. The apparatus of claim 15 , wherein each of the first command and the second command is one of read and write commands.