Integrated computing structures formed on silicon
The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.
1. A semiconductor structure, comprising:
a silicon semiconductor material comprising an integrated computing structure formed thereon; and
wherein a plurality of devices in the integrated computing structure comprises:
a p-channel field effect transistor (P-FET) that comprises a plurality of materials of a gate insulator stack and associated components;
an n-channel FET (N-FET) that comprises a plurality of materials of a gate insulator stack and associated components; and
a non-volatile memory (NVM) device that comprises a plurality of materials of a device stack and associated components;
wherein the plurality of materials of the P-FET and N-FET gate insulator stacks and associated components and the plurality of materials of the NVM device stack and associated components share a plurality of same materials at a plurality of corresponding positions within the structure to provide a particular function in all of:
an interface stabilizing material of the stacks contiguous to the silicon semiconductor material;
a metal gate interface component contiguous to a metal gate component distal from the silicon semiconductor material and between the interface stabilizing material and the metal gate component; and
a dielectric material with a high dielectric constant configured to provide a tunneling function formed contiguous to the interface stabilizing material and between the metal gate interface component and the interface stabilizing material, wherein the dielectric material is different from the interface stabilizing material.
2. The semiconductor structure of claim 1 , wherein the metal gate component comprises:
a control gate component of each of the P-FET and N-FET gate insulator stacks and the NVM device stack; and
a source gate component and a drain gate component of each of the P-FET and N-FET gate insulator stacks and the NVM device stack.
3. The semiconductor structure of claim 1 , wherein a shared same material that provides a function of the metal gate component is a same metal selected from one of tungsten (W) and aluminum (Al).
4. The semiconductor structure of claim 1 , wherein a shared same material that provides a function of the metal gate interface component is a same conductor selected from one of tantalum nitride (TaN) and titanium nitride (TiN).
5. The semiconductor structure of claim 1 , wherein a shared same material that provides a function of the interface stabilizing material is a same dielectric selected from one of silicon oxide (SiO 2 ), silicon oxynitride (SiON), and oxygen-rich silicon oxynitride (OR-SiON) that produces and stabilizes a threshold of channel formation in the silicon semiconductor material.
6. The semiconductor structure of claim 1 , further comprising a shared same high dielectric constant (k) material that provides a low leakage function in the P-FET and N-FET gate insulator stacks contiguous to the metal gate interface component on a side of the metal gate interface component opposite from the metal gate component.
7. The semiconductor structure of claim 6 , wherein the shared same high k material that provides the low leakage function is an aluminum oxide (Al 2 O 3 ) dielectric.
8. The semiconductor structure of claim 1 , further comprising:
a shared same material that provides a function of a diffusion contact to reduce resistance in the P-FET and N-FET components and in the NVM device components contiguous to a base of a source gate and a drain gate; and
wherein the source gate and the drain gate are each associated with a well formed in the silicon semiconductor material.
9. The semiconductor structure of claim 8 , wherein the shared same material is a same nickel silicide selected from one of NiSi, Ni 2 S i , and N i S 2 .
10. The semiconductor structure of claim 1 , wherein:
the P-FET gate insulator stack and associated components comprising the plurality of materials and the N-FET gate insulator stack and associated components comprising the plurality of materials are coupled as a complementary metal-oxide-semiconductor (CMOS) device configured to perform logical operations; and
the NVM device stack and associated components comprising the plurality of materials is configured for non-volatile storage of data values.
11. A method of forming a semiconductor structure, comprising:
forming a silicon semiconductor material comprising an integrated computing structure formed thereon;
wherein a plurality of devices in the integrated computing structure comprises:
forming a p-channel field effect transistor (P-FET) that comprises a plurality of materials of a gate insulator stack and associated components;
forming an n-channel FET (N-FET) that comprises a plurality of materials of a gate insulator stack and associated components; and
forming a non-volatile memory (NVM) device that comprises a plurality of materials of a device stack and associated components;
wherein the plurality of materials of the P-FET and N-FET gate insulator stacks and associated components and the plurality of materials of the NVM device stack and associated components share a plurality of same materials at a plurality of corresponding positions within the structure to provide a particular function in all of:
an interface stabilizing material of the stacks contiguous to the silicon semiconductor material;
a metal gate interface component contiguous to a metal gate component distal from the silicon semiconductor material and between the interface stabilizing material and the metal gate component; and
a dielectric material with a high dielectric constant configured to provide a tunneling function formed contiguous to the interface stabilizing material and between the metal gate interface component and the interface stabilizing material, wherein the dielectric material is different from the interface stabilizing material.
12. The method of claim 11 , wherein the metal gate component comprises:
forming a control gate component of each of the P-FET and N-FET gate insulator stacks and the NVM device stack; and
forming a source gate component and a drain gate component of each of the P-FET and N-FET gate insulator stacks and the NVM device stack.
13. The method of claim 11 , further comprising selecting a same metal as a shared same material that provides a function of the metal gate component from one of tungsten (W) and aluminum (Al).
14. The method of claim 11 , further comprising selecting a same conductor as a shared same material that provides a function of the metal gate interface component from one of tantalum nitride (TaN) and titanium nitride (TiN).
15. The method of claim 11 , further comprising selecting a same dielectric as a shared same material that provides a function of the interface stabilizing material from one of silicon oxide (SiO 2 ), silicon oxynitride (SiON), and oxygen-rich silicon oxynitride (OR-SiON) to produce and stabilize a threshold of channel formation in the silicon semiconductor material.
16. The method of claim 11 , further comprising forming a shared same high dielectric constant (k) material that provides a low leakage function in the P-FET and N-FET gate insulator stacks contiguous to the metal gate interface component on a side of the metal gate interface component opposite from the metal gate component.
17. The method of claim 16 , further comprising forming the shared same high k material that provides the low leakage function from an aluminum oxide (Al 2 O 3 ) dielectric.
18. The method of claim 11 , further comprising:
forming a shared same material that provides a function of a diffusion contact to reduce resistance in the P-FET and N-FET components and in the NVM device components contiguous to a base of a source gate and a drain gate;
wherein the source gate and the drain gate are each associated with a well formed in the silicon semiconductor material.
19. The method of claim 18 , further comprising selecting the shared same material as a same nickel silicide from one of NiSi, Ni 2 S i , and N i S 2 .
20. The method of claim 11 , further comprising:
coupling the P-FET gate insulator stack and associated components comprising the plurality of materials and the N-FET gate insulator stack and associated components comprising the plurality of materials as a complementary metal-oxide-semiconductor (CMOS) device configured to perform logical operations;
wherein the NVM device stack and associated components comprising the plurality of materials is configured for non-volatile storage of data values.