Methods for isolating portions of a loop of pitch-multiplied material and related structures
View Patent ↗Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.
1. An integrated circuit, comprising:
a plurality of loops formed of semiconductor material, each loop being defined by a pair of elongated portions joined at first and second opposing ends of the elongated portions, and each loop having a first pair of associated isolation transistors comprising a first transistor and a second transistor, the first transistor comprising:
a first active area formed in the associated loop;
a first gate disposed over the active area; and
a first source/drain region formed in the associated loop, the first gate and the first source/drain region being shunted together; and
the second transistor comprising:
a second active area formed in the associated loop;
a second gate disposed over the active area; and
a second source/drain region formed in the associated loop, the second gate and the second source/drain region being shunted together.
2. The integrated circuit of claim 1 , wherein the first transistor is proximate a first end of the associated loop and the second transistor is proximate a second end of the associated loop.
3. The integrated circuit of claim 2 , wherein the first pair of associated isolation transistors is disposed along a first of the elongated portions of each loop,
wherein each loop further has a second pair of associated isolation transistors disposed along a second of the elongated portions of each loop, the second pair of associated isolation transistors comprising a third transistor proximate the first end of the associated loop and a fourth transistor proximate the second end of the associated loop, each isolation transistor of the second pair of associated isolation transistors having a respective source/drain region shunted to a respective transistor gate.
4. The integrated circuit of claim 1 , wherein the integrated circuit is a memory device, wherein the loops of semiconductor material each form bit lines.
5. The integrated circuit of claim 1 , further comprising a pair of select transistors along each elongated portion, a first select transistor of the pair of select transistors proximate a first end of the associated loop and a second select transistor of the pair of select transistors is proximate the second end of the associated loop.
6. The integrated circuit of claim 5 , further comprising a plurality of floating gate transistors disposed along each elongated portion and between each pair of select transistors.
7. The integrated circuit of claim 1 , wherein ends of the loops extend into a periphery region of the integrated circuit.