IP Library Granted Patent US 10,923,448
Granted Patent B2
US 10,923,448 · App. 15/627,314 · Granted Feb 16, 2021

Bond pad with micro-protrusions for direct metallic bonding

Inventors: Aibin Yu (Singapore, SG); Wei Zhou (Singapore, SG); Zhaohui Ma (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L24/14H01L21/76898H01L23/00H01L23/481H01L24/00H01L24/03H01L24/05H01L24/08H01L24/09H01L24/13H01L24/80H01L24/81H01L2224/03462H01L2224/03464H01L2224/03616H01L2224/05078H01L2224/05552H01L2224/05572H01L2224/05624H01L2224/05644H01L2224/05647H01L2224/08147H01L2224/1701H01L2224/80203H01L2224/80357H01L2224/80895H01L2924/01029
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,923,448
App. No.
15/627,314
Granted
Feb 16, 2021
Kind
B2
Abstract

A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

Claims (19)

1. A bonded semiconductor assembly comprising:

a first semiconductor substrate comprising a first through-silicon via (TSV) and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side;

a second semiconductor substrate opposite to the first substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side;

a plurality of copper connecting elements, each copper connecting element physically contacting the first coupling side of the first copper pad and physically contacting the second coupling side of the second copper pad; and

a single homogenous structure of dielectric material at least partially underlying the first copper pad, at least partially overlying the first copper pad, and surrounding and physically contacting each of the plurality of copper connecting elements.

2. The bonded semiconductor assembly of claim 1 , wherein the first TSV comprises copper.

3. The bonded semiconductor assembly of claim 1 , wherein the plurality of copper connecting elements comprise pillars.

4. The bonded semiconductor assembly of claim 1 , wherein the plurality of copper connecting elements comprise at least four copper connecting elements.

5. The bonded semiconductor assembly of claim 1 , wherein the plurality of copper connecting elements each has a cross-sectional dimension of between 0.5 and 5 microns.

6. The bonded semiconductor assembly of claim 1 , wherein each of the plurality of copper connecting elements is in electrical communication with both the first and second copper pads.

7. The bonded semiconductor assembly of claim 1 , wherein each copper connecting element is configured to deform at an upper portion thereof to provide direct metal-to-metal bonding between the upper portion thereof and the second coupling side of the second copper pad.

8. A semiconductor device, comprising:

a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, a first bonding feature physically contacting and projecting away from the first pad, wherein the first bonding feature covers only a first portion of the first pad, and a second bonding feature physically contacting and projecting away from the first pad, wherein the second bonding feature covers only a second portion of the first pad;

a second semiconductor substrate having a second TSV and a second pad electrically coupled to the second TSV; and

a single homogenous structure of dielectric material disposed at least partially under the first pad between the first pad and the second pad, and surrounding and physically contacting each of the first bonding feature and the second bonding feature,

wherein each of the first bonding feature and the second bonding feature is directly physically connected to the second pad by a metal-to-metal bond.

9. The semiconductor device of claim 8 , wherein the first and second pads each comprises copper, and wherein the first and second bonding features comprise copper.

10. The semiconductor device of claim 8 , wherein the first and second bonding feature each has a cross-sectional dimension of between 0.5 and 5 microns.

11. The semiconductor device of claim 8 , wherein each of the first bonding feature and the second bonding feature is configured to deform at an upper portion thereof to provide the metal-to-metal bond between the upper portion thereof and the second pad.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2017
From: YU, AIBIN; ZHOU, WEI; MA, ZHAOHUI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042752/0102 →
Cited By (1)
US 12,444,672