Memory plate segmentation to reduce operating power
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.
1. An electronic memory apparatus comprising:
a plurality of plate portions separated by a plurality of segmentation lines, the plurality of segmentation lines comprising a first set of segmentation lines extending in a first direction and segmenting one or more plate lines;
at least one memory cell disposed on each of the plurality of plate portions, each of the plurality of plate portions being coupled to a same sense component via one of a plurality of digit lines extending in the first direction, wherein the plurality of digit lines are separate from the plurality of segmentation lines; and
a plate driver component comprising a plurality of plate drivers, each of the plurality of plate drivers being connected to one of the plurality of plate portions by a respective plate line of the one or more plate lines.
2. The electronic memory apparatus of claim 1 , wherein the plurality of segmentation lines further comprise a second set of segmentation lines extending in a second direction perpendicular to the first direction.
3. The electronic memory apparatus of claim 1 , wherein the at least one memory cell comprises a ferroelectric capacitor.
4. The electronic memory apparatus of claim 1 , further comprising a memory controller coupled to the plate driver component.
5. The electronic memory apparatus of claim 4 , wherein the memory controller is configured to activate one of the plurality of plate portions based at least in part on a location of a target memory cell.
6. The electronic memory apparatus of claim 5 , wherein the memory controller is configured to activate the one of the plurality of plate portions while setting a plurality of other plate portions to a deactivated state.
7. The electronic memory apparatus of claim 1 , further comprising:
a row decoder; and
a plurality of word lines coupling the row decoder to the at least one memory cell disposed on each of the plurality of plate portions.
8. An electronic memory apparatus comprising:
a plurality of plate portions separated by a plurality of segmentation lines, the plurality of segmentation lines comprising a first set of segmentation lines extending in a first direction and a second set of segmentation lines extending in a second direction perpendicular to the first direction;
at least one memory cell disposed on each of the plurality of plate portions, each of the plurality of plate portions being coupled to a same sense component via one of a plurality of digit lines, wherein the plurality of digit lines are separate from the plurality of segmentation lines; and
a plate driver component comprising a plurality of plate drivers, each of the plurality of plate drivers being connected to at least one of the plurality of plate portions by a respective plate line of a plurality of plate lines.
9. The electronic memory apparatus of claim 8 , wherein the at least one memory cell comprises a ferroelectric capacitor.
10. The electronic memory apparatus of claim 8 , further comprising a memory controller coupled to the plate driver component.
11. The electronic memory apparatus of claim 10 , wherein the memory controller is configured to activate one of the plurality of plate portions based at least in part on a location of a target memory cell.
12. The electronic memory apparatus of claim 8 , further comprising:
a row decoder; and
a plurality of word lines coupling the row decoder to the at least one memory cell disposed on each of the plurality of plate portions.
13. The electronic memory apparatus of claim 12 , wherein the plurality of word lines comprises at least one dummy line, the at least one dummy line electrically isolated from cells of the apparatus and located adjacent an edge of at least one of the plurality of plate portions.
14. The electronic memory apparatus of claim 8 , wherein:
the plurality of plate portions are arranged in a plurality of columns and a plurality, of rows;
each of the plurality of plate drivers is coupled to a plate portion in each of the plurality of rows; and
each of the plurality of plate drivers is coupled to a plate portion in at least two of the plurality of columns.
15. The electronic memory apparatus of claim 14 , wherein each of the plurality of plate drivers is coupled to a plate portion in each of the plurality of columns.
16. A method, comprising:
determining a location of a target memory cell; and
activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by segmentation lines and coupled to a same sense component as a plurality of plate portions via one of a plurality of digit lines, wherein the plurality of digit lines are separate from the segmentation lines, the segmentation lines comprising a first set of segmentation lines extending in a vertical direction and segmenting one or more plate lines.
17. The method of claim 16 , further comprising setting a plurality of other plate portions to a deactivated state.
18. The method of claim 16 , wherein activating the plate portion comprises applying a first voltage to a plate line coupled to the plate portion.
19. The method of claim 16 , further comprising applying a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to the digit line extending in the vertical direction.
20. The method of claim 19 , further comprising determining a logic value associated with the target memory cell based on a second voltage on the digit line.
21. The method of claim 19 , further comprising applying a second voltage to the digit line to set a logic value associated with the target memory cell.
22. A method, comprising:
determining a location of a target memory cell; and
activating, by a plate driver, a plate portion corresponding to the location of the target memory cell, the plate portion being separated from a plurality of other plate portions by segmentation lines and coupled to a same sense component as a plurality of plate portions via one of a plurality of digit lines, wherein the plurality of digit lines are separate from the segmentation lines, the segmentation lines comprising a first set of segmentation lines extending in a first direction and a second set of segmentation lines extending in a second direction perpendicular to the first direction.
23. The method of claim 22 , wherein activating the plate portion comprises applying a first voltage to a plate line coupled to the plate portion.
24. The method of claim 22 , further comprising applying a first voltage to a word line coupled to a memory cell disposed on the plate portion to connect the target memory cell to Flail the digit line extending in the first direction.
25. The method of claim 24 , further comprising determining a logic value associated with the target memory cell based on a second voltage on the digit line or applying a second voltage to the digit line to set a logic value associated with the target memory cell.
26. An electronic memory apparatus, comprising:
a plurality of plate portions separated by a plurality of segmentation lines, the plurality of segmentation lines comprising a first set of segmentation lines extending in a first direction and a second set of segmentation lines extending in a second direction perpendicular to the first direction;
a plate driver component comprising a plurality of plate drivers coupled to the plurality of plate portions, each of the plurality of plate portions being coupled to a same sense component via one of a plurality of digit lines extending in the first direction, wherein the plurality of digit lines are separate from the first set of segmentation lines and the second set of segmentation lines; and
a controller in electronic communication with the plate driver component, wherein the controller is operable to cause the apparatus to:
identify a location of a target memory cell; and
activate one of the plurality of plate portions corresponding to the location of the target cell.
27. The apparatus of claim 26 , wherein the controller is further operable to cause the apparatus to apply a first voltage to a word line coupled to the target memory cell to connect the target memory cell to a digit line.
28. The apparatus of claim 27 , wherein the controller is further operable to cause the apparatus to determine a logic value associated with the target memory cell based on a second voltage on the digit line.
29. The apparatus of claim 27 , wherein the controller is further operable to cause the apparatus to apply a second voltage to the digit line to set a logic value associated with the target memory cell.
30. The apparatus of claim 1 , wherein the plate driver component is coupled with each of the plurality of plate portions.
31. The apparatus of claim 1 , wherein each of the plurality of plate portions is common to a respective plurality of memory cells and is coupled with at least one plate line of the one or more plate lines.