Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells
A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
1. A method of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells, comprising:
forming an elevationally-inner tier of line constructions comprising spaced-lower-first-conductive lines, programmable material directly above the inner-tier-lower-first-conductive lines, and insulator material over sidewalls of the inner-tier-lower-first-conductive lines and over sidewalls of the inner-tier-programmable material;
forming an elevationally-outer tier of line constructions comprising spaced-lower-first-conductive lines, spaced-programmable-material lines directly above the outer-tier-lower-first-conductive lines, and insulative material over sidewalls of the outer-tier-lower-first-conductive lines and over sidewalls of the outer-tier-programmable-material lines; individual of the outer-tier-lower-first-conductive lines being laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions, the forming of the outer-tier-line constructions comprising:
forming at least lowermost portions of the outer-tier-lower-first-conductive lines in a self-aligned manner by depositing conductive material laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions;
forming the outer-tier-programmable material directly above the conductive material;
patterning at least the outer-tier-programmable material to form lines thereof that are directly above the lowermost portions of the outer-tier-lower-first-conductive lines; and
forming the insulative material over tops and the sidewalls of the outer-tier-programmable material lines and then anisotropically etching the insulative material to remove it from being over the tops; and
forming spaced-upper-second-conductive lines for each of an elevationally-outer tier of memory cells and an elevationally-inner tier of memory cells.
2. The method of claim 1 wherein the inner-tier-programmable material is formed to comprise spaced-programmable-material lines at least prior to forming the outer-tier-line constructions.
3. The method of claim 1 comprising forming the upper-second-conductive lines to be a single set of such lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells.
4. The method of claim 1 comprising forming uppermost portions of the outer-tier-lower-first-conductive lines in a non-self-aligned manner by patterning an uppermost portion of the deposited conductive material that is higher than the inner tier-line constructions using a mask.
5. The method of claim 1 comprising forming all of the outer-tier-lower-first-conductive lines in said self-aligned manner.
6. The method of claim 1 comprising etching through the outer-tier-programmable-material lines after the anisotropically etching of the insulative material.
7. A method of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells, comprising:
forming an elevationally-inner tier of line constructions comprising spaced-lower-first-conductive lines, programmable material directly above the inner-tier-lower-first-conductive lines, and insulator material over sidewalls of the inner-tier-lower-first-conductive lines and over sidewalls of the inner-tier-programmable material;
forming an elevationally-outer tier of line constructions comprising spaced-lower-first-conductive lines, programmable material directly above the outer-tier-lower-first-conductive lines, and insulative material over sidewalls of the outer-tier-lower-first-conductive lines and over sidewalls of the outer-tier-programmable material; individual of the outer-tier-lower-first-conductive lines being laterally between and longitudinally-elongated parallel with immediately-adjacent of the inner-tier-line constructions;
forming conductor material above and laterally between immediately-adjacent of the outer-tier-line constructions, the conductor material being electrically coupled to each of the inner-tier-programmable material and the outer-tier-programmable material; and
patterning the conductor material to form spaced-upper-second-conductive lines for each of an elevationally-outer tier of memory cells and an elevationally-inner tier of memory cells that comprise a single set of the upper-second-conductive lines that are electrically shared by the elevationally-outer-tier memory cells and the elevationally-inner-tier memory cells.
8. The method of claim 7 wherein the inner-tier-programmable material is formed to comprise spaced-programmable-material lines at least prior to forming the outer tier line constructions.
9. The method of claim 7 wherein the inner-tier-programmable material is formed to comprise spaced-programmable-material lines at least prior to forming the outer tier line constructions and the outer-tier-programmable material is formed to comprise spaced-programmable-material lines at least prior to forming the conductor material; and
further comprising etching through the outer-tier-programmable-material lines and into the inner-tier-line constructions using at least the spaced-upper-second-conductive lines as a mask.
10. The method of claim 7 wherein the outer-tier-programmable material is formed to comprise spaced-programmable-material lines at least prior to forming the conductor material.
11. The method of claim 10 further comprising etching through the outer-tier-programmable-material lines using at least the spaced-upper-second-conductive lines as a mask.
12. The method of claim 11 comprising also using masking material above the spaced-upper-second-conductive lines as the mask.
13. A method of forming an array of memory cells, the array comprising an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, the method comprising:
depositing conductor material for all of the shared-spaced-upper-second-conductive lines, the conductor material being deposited aside the outer-tier-programmable material; and
patterning all of the conductor material for all of the shared-spaced-upper-second-conductive lines using only a single masking step.
14. The method of claim 13 comprising forming the upper-second-conductive lines directly above the inner-tier-programmable material.
15. The method of claim 13 comprising conducting said patterning with the single mask after forming the inner-tier-lower-first-conductive lines and after forming the outer-tier-lower-first-conductive lines.
16. The method of claim 13 comprising conducting said patterning with the single mask after forming the inner-tier-programmable material and after forming the outer-tier-programmable material.
17. A method of forming an array of memory cells, the array comprising an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, the method comprising:
depositing conductor material for all of the shared-spaced-upper-second-conductive lines;
patterning all of the conductor material for all of the shared-spaced-upper-second-conductive lines using only a single masking step; and
forming the upper-second-conductive lines directly above the outer-tier-programmable material.
18. A method of forming an array of memory cells, the array comprising an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, the method comprising:
depositing conductor material for all of the shared-spaced-upper-second-conductive lines;
patterning all of the conductor material for all of the shared-spaced-upper-second-conductive lines using only a single masking step; and
the spaced-upper-second-conductive lines being directly above both of the inner-tier-programmable material and the outer-tier-programmable material.