Access line management for an array of memory cells
View Patent ↗Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
1. A method, comprising:
driving a plate coupled with at least a first memory cell of an array of memory cells to a first voltage;
identifying an access operation associated with a second memory cell of the array of memory cells;
floating, for a duration, a first access line coupled with the first memory cell of the array of memory cells based at least in part on the access operation associated with the second memory cell;
driving, during the duration, the plate from the first voltage to a second voltage based at least in part on the access operation associated with the second memory cell; and
driving the first access line, after the duration, to a desired voltage based at least in part on a difference between the first voltage and the second voltage.
2. The method of claim 1 , further comprising:
driving the plate from the second voltage to the first voltage; and
floating the first access line after driving the first access line to the desired voltage while driving the plate from the second voltage to the first voltage.
3. The method of claim 1 , further comprising:
driving a second access line coupled with the second memory cell to a third voltage during the duration.
4. A method, comprising:
driving a plate coupled with at least a first memory cell of an array of memory cells to a first voltage;
identifying an access operation associated with a second memory cell of the array of memory cells;
floating, for a duration, a first access line coupled with the first memory cell of the array of memory cells based at least in part on the access operation associated with the second memory cell;
driving, during the duration, the plate from the first voltage to a second voltage based at least in part on the access operation associated with the second memory cell;
driving a second access line coupled with the second memory cell to a third voltage during the duration; and
driving a third access line coupled with a third memory cell to a fourth voltage during the duration while driving the plate from the first voltage to the second voltage.
5. A method, comprising:
driving a plate coupled with at least a first memory cell of an array of memory cells to a first voltage;
identifying an access operation associated with a second memory cell of the array of memory cells;
floating, for a duration, a first access line coupled with the first memory cell of the array of memory cells based at least in part on the access operation associated with the second memory cell;
driving, during the duration, the plate from the first voltage to a second voltage based at least in part on the access operation associated with the second memory cell; and
floating the first access line for a second duration immediately subsequent to the duration.
6. The method of claim 1 , wherein the plate is coupled with a plurality of memory cells of the array of memory cells, the plurality of memory cells comprising the first memory cell and the second memory cell.
7. The method of claim 1 , wherein the plate is coupled with multiple rows or multiple columns of memory cells of a first deck of the array of memory cells and with multiple rows or multiple columns of memory cells of a second deck of the array of memory cells.
8. The method of claim 1 ,
wherein floating the first access line and driving the plate to the second voltage occur concurrently.
9. An apparatus, comprising:
an array of memory cells that includes a first memory cell and a second memory cell;
a first access line coupled with the first memory cell;
an access line driver coupled with the first access line, the access line driver configured to float the first access line during a duration based at least in part on an access operation associated with the second memory cell;
a plate coupled with the first memory cell and the second memory cell;
a plate line driver coupled with the plate, the plate line driver configured to drive the plate to a first voltage before the duration, and drive the plate to a second voltage during the duration based at least in part on the access operation associated with the second memory cell; and
the access line driver is further configured to drive the first access line to a desired voltage after the duration based at least in part on a difference between the first voltage and the second voltage.
10. The apparatus of claim 9 , wherein the first access line comprises an unselected access line.
11. The apparatus of claim 9 , wherein a second access line coupled with the second memory cell, the second access line comprising a selected access line.
12. The apparatus of claim 11 , wherein the access line driver is coupled with the second access line and further configured to drive the second access line to a third voltage, the third voltage associated with a first logic value of the second memory cell.
13. An apparatus, comprising:
an array of memory cells that includes a first memory cell and a second memory cell;
a first access line coupled with the first memory cell;
an access line driver coupled with the first access line, the access line driver configured to float the first access line during a duration based at least in part on an access operation associated with the second memory cell;
a plate coupled with the first memory cell and the second memory cell;
a plate line driver coupled with the plate, the plate line driver configured to drive the plate to a first voltage before the duration, and drive the plate to a second voltage during the duration based at least in part on the access operation associated with the second memory cell;
a second access line coupled with the second memory cell, the second access line comprising a selected access line; and
a third access line coupled with a third memory cell, the third access line comprising an unselected access line, wherein the access line driver is coupled with the second access line and the third access line.
14. The apparatus of claim 13 , wherein the access line driver is further configured to:
drive the second access line a fourth voltage, the fourth voltage associated with a first logic value of the second memory cell; and
drive the third access line to a fifth voltage, the fifth voltage associated with a second logic value of the third memory cell.
15. The apparatus of claim 9 , wherein the access line driver is further configured to continue floating the first access line after the duration.
16. The apparatus of claim 9 , where the array of memory cells comprises a plurality of ferroelectric memory cells.
17. An apparatus, comprising:
a plate coupled with a plurality of memory cells that includes a first memory cell and a second memory cell;
a plate driver coupled with the plate;
a first access line coupled with the first memory cell;
an access line driver coupled with the first access line;
a controller configured to:
identify an access operation associated with the second memory cell;
initiate driving the plate from a first voltage to a second voltage based at least in part on the access operation associated with the second memory cell;
initiate floating the first access line based at least in part on the access operation associated with the second memory cell; and
initiate driving the first access line to a desired voltage after the plate is at the second voltage based at least in part on a difference between the first voltage and the second voltage.
18. The apparatus of claim 17 , wherein the controller is further configured to continue floating the first access line after the plate is at the second voltage.
19. The apparatus of claim 17 , wherein the controller is further configured to concurrently initiate floating the first access line and driving the plate to the second voltage.
20. The apparatus of claim 17 , wherein the controller is further configured to initiate floating the first access line before initiating driving the plate to the second voltage.
21. The apparatus of claim 17 , wherein the controller is further configured to initiate selecting a second access line coupled with the second memory cell based at least in part on the access operation associated with the second memory cell.
22. An apparatus, comprising:
a plate coupled with a plurality of memory cells that includes a first memory cell and a second memory cell;
a plate driver coupled with the plate;
a first access line coupled with the first memory cell;
an access line driver coupled with the first access line;
a controller configured to:
identify an access operation associated with the second memory cell;
initiate driving the plate from a first voltage to a second voltage based at least in part on the access operation associated with the second memory cell;
initiate floating the first access line based at least in part on the access operation associated with the second memory cell;
initiate selecting a second access line coupled with the second memory cell based at least in part on the access operation associated with the second memory cell; and
initiate driving a third access line associated with a third memory cell of the plurality of memory cells to a third voltage based at least in part on the access operation associated with the second memory cell.
23. The method of claim 5 , wherein the plate is coupled with a plurality of memory cells of the array of memory cells, the plurality of memory cells comprising the first memory cell and the second memory cell.
24. The method of claim 5 , wherein the plate is coupled with multiple rows or multiple columns of memory cells of a first deck of the array of memory cells and with multiple rows or multiple columns of memory cells of a second deck of the array of memory cells.
25. The method of claim 5 ,
wherein floating the first access line and driving the plate to the second voltage occur concurrently.