Communicating data with stacked memory dies
Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
1. A method, comprising:
receiving, from a host device, a first signal modulated using a first modulation scheme that includes two levels;
generating, by a first comparator, a third signal comprising one or more even bits of the first signal based at least in part on receiving the first signal;
generating, by a second comparator, a fourth signal comprising one or more odd bits of the first signal based at least in part on receiving the first signal;
generating, by a multiplexer at a memory controller and based at least in part on generating the third signal and the fourth signal, a second signal modulated using a second modulation scheme that includes three or more levels; and
transmitting the second signal to a first memory die and a second memory die of a first plurality of memory dies that are coupled with the memory controller over a first through-silicon via (TSV) and to a second plurality of memory dies over a second TSV and a third TSV, wherein the first TSV is coupled with the first memory die and the second memory die, the second TSV is coupled with each memory die of the second plurality of memory dies, and the third TSV bypasses the first plurality of memory dies and is coupled with a repeater and the memory controller, and wherein the second signal is concurrently present at the first memory die of the first plurality of memory dies, the second memory die of the first plurality of memory dies via the first TSV, and the second plurality of memory dies based at least in part on the third TSV relaying the second signal to the repeater and the repeater relaying the second signal to the second plurality of memory dies via the second TSV, and wherein the first TSV is coupled with the repeater and the memory controller.
2. The method of claim 1 , wherein:
the first signal is encoded with a modulation scheme comprising two levels; and
the second signal is encoded with a pulse-amplitude modulation (PAM) scheme comprising three or more levels.
3. The method of claim 1 , further comprising:
deserializing the first signal after receiving the first signal, wherein generating the second signal is based at least in part on deserializing the first signal.
4. The method of claim 1 , further comprising:
decoding the second signal at one memory die of the first plurality of memory dies, wherein each memory die of the first plurality of memory dies comprises a receiver configured to decode the second signal.
5. The method of claim 1 , further comprises:
capturing a first subset of information from the first signal using a first clock signal;
capturing a second subset of information from the first signal using a second clock signal; and
aligning in time the first subset of information and the second subset of information, wherein generating the second signal is based at least in part on aligning the first subset of information and the second subset of information.
6. The method of claim 1 , wherein the second signal is relayed, by the repeater that is coupled with the third TSV and the second TSV, to the second plurality of memory dies.
7. The method of claim 6 , wherein the first plurality of memory dies are stacked on top of each other.
8. The method of claim 1 , further comprising:
generating a fifth signal based at least in part on generating the second signal; and
transmitting the fifth signal to the first memory die and the second memory die of the first plurality of memory dies concurrently with transmitting the second signal.
9. The method of claim 8 , wherein the fifth signal comprises a Chip Enable (CE) signal.
10. The method of claim 1 , wherein:
the first signal is received via a first internal signal path that is dedicated to communicating signals modulated with the first modulation scheme; and
the second signal is transmitted via a second internal signal path dedicated to communicating signals modulated with the second modulation scheme.
11. The method of claim 1 , wherein generating the second signal comprises:
multiplexing first data and second data into one or more symbols of the second signal, wherein a first bit of a symbol of the second signal is associated with the first data and intended for a memory die of the first plurality of memory dies and a second bit of the symbol is associated with the second data and intended for a memory die of the second plurality of memory dies.
12. A method, comprising:
generating, at a memory controller and based at least in part on information received from a host device, a first signal modulated using a first modulation scheme that includes three or more levels;
generating, by a first comparator, a third signal comprising one or more even bits of the first signal based at least in part on receiving the first signal;
generating, by a second comparator, a fourth signal comprising one or more odd bits of the first signal based at least in part on receiving the first signal;
generating, by a multiplexer at the memory controller, a second signal modulated using a second modulation scheme that includes three or more levels based at least in part on generating the third signal and the fourth signal, wherein the second signal comprises an indicator of a designated memory die targeted to receive the first signal; and
transmitting, based at least in part on generating the second signal, the first signal and the second signal concurrently to one or more memory dies of a first plurality of memory dies that are coupled with the memory controller over a first through-silicon via (TSV) and to a second plurality of memory dies over a second TSV and a third TSV, wherein the first TSV is coupled with a first memory die of the first plurality of memory dies and a second memory die of the first plurality of memory dies, the second TSV is coupled with each memory die of the second plurality of memory dies, and the third TSV bypasses the first plurality of memory dies and is coupled with a repeater and the memory controller, and wherein the second signal is concurrently present at the first memory die of the first plurality of memory dies, the second memory die of the first plurality of memory dies, and the second plurality of memory dies based at least in part on the third TSV relaying the second signal to the repeater and the repeater relaying the second signal to the second plurality of memory dies via the second TSV, and wherein the first TSV is coupled with the repeater and the memory controller.
13. The method of claim 12 , wherein generating the second signal comprises:
encoding the second signal with a pulse-amplitude modulation (PAM) scheme.
14. The method of claim 13 , further comprising:
decoding the second signal at the one or more memory dies of the first plurality of memory dies.
15. The method of claim 14 , further comprising:
activating a first receiver of the one or more memory dies based at least in part on decoding the second signal, wherein the first receiver is configured to decode the first signal.
16. The method of claim 15 , further comprising:
decoding the first signal at the one or more memory dies based at least in part on activating the first receiver.
17. The method of claim 12 , further comprising:
configuring an interior data bus within a memory die of the first plurality of memory dies to carry a signal modulated using a modulation scheme that includes three or more levels.
18. The method of claim 12 , wherein the first modulation scheme includes two levels, the first signal comprises metadata, and the second signal comprises control data.
19. An apparatus, comprising:
a first plurality of memory dies, one or more memory dies of the first plurality of memory dies comprising a first through-silicon via (TSV);
a second plurality of memory dies, one or more memory dies of the second plurality of memory dies comprising a second TSV;
a bus coupled with the first TSV and a third TSV that bypasses the first plurality of memory dies and is coupled with a repeater and a controller; and
the controller coupled with the first plurality of memory dies, the controller operable to:
generate, by a first comparator, a third signal comprising one or more even bits of a first signal based at least in part on receiving the first signal;
generate, by a second comparator, a fourth signal comprising one or more odd bits of the first signal based at least in part on receiving the first signal;
generate, by a multiplexer, based at least in part on the first signal modulated using a first modulation scheme that includes two levels and generating the third signal and the fourth signal, a second signal modulated using a second modulation scheme that includes three or more levels; and
transmit the second signal to a first memory die and a second memory die of the first plurality of memory dies over the first TSV and to the second plurality of memory dies over the second TSV and the third TSV, wherein the first TSV is coupled with the first memory die and the second memory die, the second TSV is coupled with the second plurality of memory dies, and the third TSV is coupled with the second TSV, and wherein the second signal is concurrently present at the first memory die of the first plurality of memory dies, the second memory die of the first plurality of memory dies, and the second plurality of memory dies based at least in part on the third TSV relaying the second signal to the repeater and the repeater relaying the second signal to the second plurality of memory dies via the second TSV, and wherein the first TSV is coupled with the repeater and the controller.
20. The apparatus of claim 19 , further comprising:
a second controller coupled with the first plurality of memory dies through the first TSV and the second plurality of memory dies through the second TSV, the second controller operable to:
receive the second signal through the first TSV; and
re-transmit the second signal to at least one memory die of the second plurality of memory dies based at least in part on receiving the second signal.
21. The apparatus of claim 20 , wherein:
the controller, during a first time duration, is operable to transmit the second signal to the one or more memory dies of the first plurality of memory dies; and
the controller, during a second time duration subsequent to the first time duration, is operable to:
transmit the second signal to the one or more memory dies of the second plurality of memory dies through the first TSV in conjunction with re-transmitting the second signal at the second controller.
22. The apparatus of claim 20 , wherein the apparatus is configured in a package-on-package stack, wherein:
the first plurality of memory dies is located above the controller;
the second controller is located above the first plurality of memory dies; and
the second plurality of memory dies is located above the second controller.
23. The apparatus of claim 19 , further comprising:
a second controller coupled with the first plurality of memory dies through the first TSV, the second plurality of memory dies through the second TSV, and the controller over the third TSV, the second controller operable to:
receive the second signal through the third TSV.
24. The apparatus of claim 23 , wherein the controller is operable to:
transmit the second signal to the one or more memory dies of the first plurality of memory dies through the first TSV and to the one or more memory dies of the second plurality of memory dies through the second TSV and the third TSV, wherein transmitting to the one or more memory dies of the second plurality of memory dies is in conjunction with re-transmitting the second signal at the second controller.
25. An apparatus, comprising:
a first plurality of memory dies comprising a first memory die and a second memory die;
a second plurality of memory dies;
a first through-silicon via (TSV) coupled with the first memory die and the second memory die;
a second TSV coupled with the second plurality of memory dies;
a third TSV that bypasses the first plurality of memory dies and is coupled with the second TSV;
a repeater that is coupled with a memory controller via the first TSV and the third TSV;
a bus that is coupled with the first TSV and the third TSV; and
the memory controller coupled with a host device, the bus, the first plurality of memory dies, and the second plurality of memory dies, wherein the memory controller is operable to:
receive, from the host device, a first signal modulated using a first modulation scheme that includes two levels;
generate, by a first comparator, a third signal comprising one or more even bits of the first signal based at least in part on receiving the first signal;
generate, by a second comparator, a fourth signal comprising one or more odd bits of the first signal based at least in part on receiving the first signal;
generate, by a multiplexer, based at least in part on generating the third signal and the fourth signal, a second signal modulated using a second modulation scheme that includes three or more levels; and
transmit the second signal to the first memory die and the second memory die over the first TSV and to the second plurality of memory dies over the second TSV and the third TSV, wherein the second signal is concurrently present at the first memory die of the first plurality of memory dies, the second memory die of the first plurality of memory dies, and the second plurality of memory dies based at least in part on the third TSV relaying the second signal to the repeater and the repeater relaying the second signal to the second plurality of memory dies via the second TSV.
26. The apparatus of claim 25 , wherein the memory controller is further operable to:
deserialize the first signal after receiving the first signal, wherein generating the second signal is based at least in part on deserializing the first signal.
27. The apparatus of claim 25 , wherein the memory controller is further operable to:
generate a fifth signal based at least in part on generating the second signal; and
transmit the fifth signal to the first memory die and the second memory die of the first plurality of memory dies concurrently with transmitting the second signal.