Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors

1. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of wordlines and columns of digitlines, comprising:

individual of the columns comprising a digitline under channel regions of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column, the channel regions individually comprising a pair of opposing lateral sides;

individual of the rows comprising a wordline above the digitlines, the wordline extending laterally across and operatively laterally adjacent one of the pair of laterally-opposing sides of the transistor channel regions and interconnecting the transistors in that row, the other of the pair of laterally-opposing sides of the transistor channel regions in that row not being operatively laterally adjacent the wordline in that row and not being operatively laterally adjacent any other of the wordlines; and

capacitors of the individual memory cells within the array individually comprising:

a first capacitor electrode electrically coupled to and extending elevationally upward from an upper source/drain region of one of the transistors;

an elevationally-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being operatively adjacent a lateral side of the first capacitor electrode; and

an elevationally-extending second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being operatively adjacent the other laterally-opposing side of the capacitor insulator, the second capacitor electrodes within the array being spaced longitudinally-elongated lines extending horizontally along lines of the capacitors, individual of the second capacitor electrode lines being shared by capacitors longitudinally along that line of capacitors.

2. The array of claim 1 wherein the one laterally-opposing side of the capacitor insulator is directly against said lateral side of the first capacitor electrode, at least a majority of the one laterally-opposing side of the capacitor insulator and said lateral side of the first capacitor electrode from top to bottom where such are directly against one another being each linearly straight in horizontal cross-section.

3. The array of claim 2 wherein all of the one laterally-opposing side of the capacitor insulator and said lateral side of the first capacitor electrode from top to bottom where such are directly against one another are each linearly straight form side-to-side in horizontal cross-section.

4. The array of claim 1 wherein the first capacitor electrode is directly against an uppermost surface of the upper source/drain region, the first capacitor electrode being directly against less-than-all of the upper source/drain region uppermost surface.

5. The array of claim 1 wherein the first capacitor electrodes individually extend longitudinally along their respective second capacitor electrode line a greater horizontal distance than horizontal distance of space between immediately-longitudinally-adjacent of the first capacitor electrodes along that line of capacitors.

6. The array of claim 1 wherein the wordlines are parallel relative one another, the second capacitor electrode lines being parallel relative one another and relative the wordlines.

7. The array of claim 1 wherein the digitlines are parallel relative one another, the second capacitor electrode lines being parallel relative one another and not being parallel relative the digitlines.

8. The array of claim 1 wherein the memory cells within a tier of the memory cells have translational symmetry where individual of the memory cells are 1T-1C and occupy a horizontal area of about 1.0667F 2 , where “F” is memory cell pitch taken horizontally, laterally, and orthogonally through individual of the second capacitor electrode lines, the capacitor insulator, and the first capacitor electrodes.

9. The array of claim 8 wherein the horizontal area is horizontally bounded by a 1F by 1.0667F rectangle.

10. The array of claim 1 wherein individual pairs of immediately-laterally-adjacent of the wordlines have at least portions thereof that are directly under the individual second capacitor electrode lines.

11. The array of claim 10 wherein the pairs of the immediately-laterally-adjacent wordlines are further laterally apart from one another than are individual of the wordlines within each pair of the immediately-laterally-adjacent wordlines.

12. The array of claim 1 wherein the second capacitor electrode lines are individually wider than the individual wordlines.

13. The array of claim 12 wherein the second capacitor electrode lines are individually more-than-twice as wide as the individual wordlines.

14. The array of claim 13 wherein the second capacitor electrode lines are individually at least five times as wide as the individual wordlines.

15. The method of claim 13 wherein the second capacitor electrodes are individually no more than five times as wide as the individual wordlines.

16. The array of claim 1 wherein the second capacitor electrode lines are individually wider than the individual digitlines.

17. The array of claim 16 wherein the second capacitor electrode lines are individually less-than-twice as wide as the individual digitlines.

18. The array of claim 1 wherein the capacitor insulator is ferroelectric.

19. The array of claim 1 wherein the transistors individually comprise:

semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem, the semiconductor material of the stem comprising individual of the upper source/drain regions and individual of the channel regions below the individual upper source/drain regions;

at least one of (a) and (b), where

(a): the semiconductor material of the stem comprises a lower source/drain region below the channel region; and

(b): the semiconductor material of the base comprises a lower source/drain region; and

a gate operatively laterally adjacent the channel region of the stem, individual of said gates being an individual portion of individual of the wordlines.

20. The array of claim 19 comprising individual pairs of immediately-laterally-adjacent transistors, one individual of the semiconductor material within each pair of the immediately-laterally-adjacent transistors being generally L-shaped in the at least one straight-line vertical cross-section, the other individual semiconductor material within each pair of the immediately-laterally-adjacent transistors being generally mirror L-shaped in the at least one straight-line vertical cross-section.

21. The array of claim 20 wherein the pairs of the immediately-laterally-adjacent transistors are further laterally apart from one another than are individual of the transistors within each pair of the immediately-laterally-adjacent transistors.

22. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of wordlines and columns of digitlines, comprising:

individual of the columns comprising a digitline under channel regions of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column, the channel regions individually comprising a pair of opposing lateral sides;

individual of the rows comprising a wordline above the digitlines, the wordline extending laterally across and operatively laterally adjacent one of the pair of laterally-opposing sides of the transistor channel regions and interconnecting the transistors in that row, the other of the pair of laterally-opposing sides of the transistor channel regions in that row not being operatively laterally adjacent the wordline in that row and not being operatively laterally adjacent any other of the wordlines; and

capacitors of the individual memory cells within the array individually comprising:

a first capacitor electrode directly against and extending elevationally upward from an uppermost surface of an upper source/drain region of one of the transistors, the first capacitor electrode being directly against less-than-all of the uppermost surface of the upper source/drain region;

an elevationally-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being operatively adjacent a lateral side of the first capacitor electrode; and

an elevationally-extending second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being operatively adjacent the other laterally-opposing side of the capacitor insulator.

23. The array of claim 22 wherein the first capacitor electrode is directly against less-than-half of all of the upper source/drain region uppermost surface.

24. The array of claim 22 wherein more-than-half of a lowermost surface of the first capacitor electrode is directly against the upper source/drain region uppermost surface.

25. The array of claim 22 wherein the memory cells within a tier of the memory cells have translational symmetry where individual of the memory cells are 1T-1C and occupy a horizontal area of about 1.0667F 2 , where “F” is memory cell pitch taken horizontally, laterally, and orthogonally through individual of the second capacitor electrode lines, the capacitor insulator, and the first capacitor electrodes.

26. The array of claim 25 wherein the horizontal area is horizontally bounded by a 1F by 1.0667F rectangle.

27. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of wordlines and columns of digitlines, comprising:

individual of the columns comprising a digitline under channel regions of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising a wordline above the digitlines, the wordline extending laterally across and operatively laterally adjacent a lateral side of the transistor channel regions and interconnecting the transistors in that row;

capacitors of the individual memory cells within the array individually comprising:

a first capacitor electrode electrically coupled to and extending elevationally upward from an upper source/drain region of one of the transistors;

an elevationally-extending capacitor insulator comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the capacitor insulator being operatively adjacent a lateral side of the first capacitor electrode; and

an elevationally-extending second capacitor electrode comprising a pair of laterally-opposing sides, one of the laterally-opposing sides of the second capacitor electrode being operatively adjacent the other laterally-opposing side of the capacitor insulator, the second capacitor electrodes within the array being spaced longitudinally-elongated lines extending horizontally along lines of the capacitors, individual of the second capacitor electrode lines being shared by capacitors longitudinally along that line of capacitors; and

individual pairs of immediately-laterally-adjacent of the wordlines having at least portions thereof that are directly under the individual second capacitor electrode lines.

28. The array of claim 27 wherein the pairs of the immediately-laterally-adjacent wordlines are further laterally apart from one another than are individual of the wordlines within each pair of the immediately-laterally-adjacent wordlines.

29. The array of claim 27 wherein the memory cells within a tier of the memory cells have translational symmetry where individual of the memory cells are 1T-1C and occupy a horizontal area of about 1.0667F 2 , where “F” is memory cell pitch taken horizontally, laterally, and orthogonally through individual of the second capacitor electrode lines, the capacitor insulator, and the first capacitor electrodes.

30. The array of claim 29 wherein the horizontal area is horizontally bounded by a 1F by 1.0667F rectangle.