IP Library Granted Patent US 10,705,747
Granted Patent B2
US 10,705,747 · App. 15/927,339 · Granted Jul 7, 2020

Latency-based storage in a hybrid memory system

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Quick Facts
Patent No.
US 10,705,747
App. No.
15/927,339
Granted
Jul 7, 2020
Kind
B2
Abstract

An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.

Claims (50)

1. A method, comprising:

assigning a sensitivity to a command associated with a main memory of a host that is separate from and coupleable to the hybrid memory system, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with the execution of the command;

determining that the command corresponds to a particular type of file system write having a determinable write pattern associated therewith; and

selectively diverting the command to a flash memory device or a phase change random access memory device of the hybrid memory system by mapping a logical block address (LBA) associated with the main memory of the host to the flash memory device or the phase change random access memory device that is configured to exhibit a lower write latency and a higher endurance when handling the command based, at least in part, on the assigned sensitivity, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable write pattern associated therewith.

2. The method of claim 1 , further comprising assigning the sensitivity to the command based on an amount of resources consumed in execution of the command, a size of the command, the frequency of execution of the command, or combinations thereof.

3. The method of claim 1 , wherein the command comprises a database management system command.

4. The method of claim 1 , further comprising:

determining that the command is characterized by a plurality of random write operations; and

selectively diverting the command to the hybrid memory system based, at least in part, on the determination that the command is characterized by the plurality of random write operations.

5. The method of claim 1 , further comprising:

determining that the command is smaller than a threshold command size; and

selectively diverting the command to the hybrid memory system based, at least in part, on the determination that the command is smaller than the threshold command size.

6. A method, comprising:

identifying a particular type of command traffic associated with a main memory of a host that is separate from and coupleable to the hybrid memory system and executed by a host;

assigning a sensitivity to a command, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with the execution of the command;

determine that the command corresponds to a particular type of file system write having a determinable write pattern associated therewith; and

causing the command traffic to be selectively diverted to a flash memory device or a phase change random access memory device of a hybrid memory system coupleable to the host by mapping a logical block address (LBA) associated with the main memory of the host to the flash memory device or the phase change random access memory device that is configured to exhibit a lower write latency and a higher endurance when handling the command based, at least in part, on the identified characteristic, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable write pattern associated therewith.

7. The method of claim 6 , wherein the particular type of command traffic is command traffic corresponding to a file system metadata update, command traffic exhibiting a repetitive write pattern, command traffic exhibiting a predictable write pattern, command traffic corresponding to a journaling file system associated with the host, or combinations thereof.

8. The method of claim 6 , further comprising identifying the particular type of command traffic based on at least one of a frequency of execution of the command traffic and a size of commands associated with the command traffic.

9. The method of claim 6 , further comprising:

determining that the command is characterized by a plurality of random write operations, that the command is smaller than a threshold command size, or combinations thereof; and

selectively diverting the command to the hybrid memory system based, at least in part, on the determination.

10. The method of claim 6 , further comprising selectively diverting the command traffic to a portion of the hybrid memory system based, at least in part, on a determination that the command traffic exhibits a specific write pattern.

11. An apparatus, comprising:

a hybrid memory system comprising a first non-volatile memory (NVM) resource, a second NVM resource, and a controller,

wherein the controller is configured to:

assign a sensitivity to a command associated with a main memory of a host that is separate from and coupleable to the hybrid memory system, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;

determine that the command corresponds to a particular type of file system write having a determinable write pattern associated therewith; and

cause the command to be selectively diverted to the first NVM or the second NVM of the hybrid memory system by mapping a logical block address (LBA) associated with the main memory of the host to the one of the first NVM or the second NVM that is configured to exhibit a lower write latency and a higher endurance when handling the command based, at least in part, on the assigned sensitivity, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable write pattern associated therewith.

12. The apparatus of claim 11 , wherein the sensitivity is based, at least in part, on a size of the command.

13. The apparatus of claim 11 , wherein the host coupleable to the hybrid memory system is configured to assign an indicator to the command based on the assigned sensitivity of the command.

14. The apparatus of claim 11 , wherein the command corresponds to a database management system command.

15. The apparatus of claim 11 , wherein the controller is further configured to:

determine the write latency associated with execution of the command; and

responsive to a determination that the write latency associated with execution of the command exceeds a particular write latency threshold, cause the command to be selectively diverted to the hybrid memory system.

16. The apparatus of claim 11 , wherein the sensitivity is based, at least in part, on an amount of resources consumed in execution of the command.

17. The apparatus of claim 11 , wherein at least one of the first NVM and the second NVM comprises a resistance variable memory device and the other of the first NVM and the second NVM comprises a flash memory device.

18. An apparatus, comprising:

a hybrid memory system comprising a first non-volatile memory (NVM) resource, a second NVM resource, and a controller,

wherein the controller is configured to:

identify a particular type of command traffic associated with a main memory of a host that is separate from and coupleable to the hybrid memory system and executed by the host;

assign a sensitivity to a command, wherein the sensitivity is based on a frequency of execution of the command and a write latency associated with execution of the command;

determine that the command corresponds to a particular type of file system write having a determinable write pattern associated therewith; and

cause the command traffic to be selectively diverted to the first NVM or the second NVM of the hybrid memory system by mapping a logical block address (LBA) associated with the main memory of the host to the one of the first NVM or the second NVM that is configured to exhibit a lower write latency and a higher endurance when handling the command based, at least in part, on the identified characteristic, the command corresponding to the particular type of file system write, and the particular type of file system write having the determinable pattern associated therewith.

19. The apparatus of claim 18 , wherein the particular type of command traffic is command traffic corresponding to a file system metadata update.

20. The apparatus of claim 18 , wherein the particular type of command traffic is command traffic that exhibits at least one of a repetitive write pattern and a predictable write pattern.

21. The apparatus of claim 18 , wherein the particular type of command traffic comprises command traffic corresponding to a file system metadata.

22. The apparatus of claim 18 , wherein the controller is further configured to identify the particular type of command traffic based on at least one of the frequency of execution of the command traffic and a size of the command traffic.

23. The apparatus of claim 18 , wherein the controller is further configured to identify the particular type of command traffic based on an amount of resources consumed in execution of the command traffic.

24. The apparatus of claim 18 , wherein the hybrid memory system comprises the first NVM and the second NVM, and wherein the first NVM is a NAND and the second NVM is a phase change memory.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2018
From: CARACCIO, DANILO; CONFALONIERI, EMANUELE; DALLABORA, MARCO; IZZI, ROBERTO; AMATO, PAOLO; BALLUCHI, DANIELE; PORZIO, LUCA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045301/0553 →