Cross-point memory array and related fabrication techniques
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
1. A method, comprising:
forming a plurality of vias through a top layer of a stack that comprises a first dielectric material at a first layer;
forming a first channel in the first dielectric material, the first channel connecting at least two of the plurality of vias:
filling the first channel with an electrode material;
forming, in the electrode material within the first channel, a second channel that is narrower than the first channel; and
filling the second channel with the first dielectric material.
2. The method of claim 1 , wherein forming the first channel comprises:
forming a plurality of first cavities in the first dielectric material.
3. The method of claim 2 , wherein contiguous first cavities merge to form the first channel.
4. The method of claim 2 , wherein forming the plurality of first cavities comprises:
removing, through the plurality of vias, a portion of the first dielectric material from the first layer.
5. The method of claim 4 , wherein removing the portion of the first dielectric material comprises:
applying an isotropic etchant that is chemically selective between the first dielectric material and at least one other material in the stack.
6. The method of claim 1 , wherein forming the second channel comprises:
forming a plurality of second cavities in the electrode material within the first channel.
7. The method of claim 6 , wherein forming the plurality of second cavities comprises:
removing, through the plurality of vias, a portion of the electrode material from the first channel.
8. The method of claim 7 , wherein removing the portion of the electrode material comprises:
applying an isotropic etchant that is chemically selective between the electrode material and at least one other material in the stack.
9. The method of claim 1 , further comprising:
forming a conformal liner within the first channel, the conformal liner interposed between the first dielectric material and the electrode material.
10. The method of claim 1 , wherein the stack further comprises:
a second layer comprising a second dielectric material; and
a third layer between the first layer and the second layer, the third layer comprising a chalcogenide material.
11. The method of claim 1 , further comprising:
forming a plurality of second vias through the top layer of the stack, wherein the plurality of second vias form a second row of vias that intersects a first row of vias formed by the plurality of vias, and wherein the stack comprises a second dielectric material at a second layer;
forming a third channel in the second dielectric material that connects the plurality of second vias;
filling the third channel with the electrode material;
forming, in the electrode material within the third channel, a fourth channel that is narrower than the third channel; and
filling the fourth channel with the second dielectric material.
12. The method of claim 1 , wherein filling the second channel with the first dielectric material creates a loop of electrode material at the first layer.