Indication in memory system or sub-system of latency associated with performing an access command
View Patent ↗Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
1. A method, comprising:
receiving, from a host, a read command for a set of data at a memory device;
determining that the set of data is absent from a buffer within the memory device; and
sending, to the host, an indication of a time delay for the host to observe before issuing a subsequent access command based at least in part on the set of data being absent from the buffer, wherein sending the indication of the time delay for the host to observe comprises transmitting one or more pulses on a pin of the memory device.
2. The method of claim 1 , further comprising:
determining an activity level of a memory array associated with the buffer; and
determining a duration of the time delay based at least in part on the activity level of the memory array.
3. The method of claim 1 , wherein a duration of the time delay is preconfigured at the host.
4. The method of claim 1 , wherein a duration of the time delay is indicated by a quantity of pulses, a pulse duration, or a pulse pattern, or any combination thereof.
5. The method of claim 1 , wherein the pin is designated for command or control information and configured to signal, to the host, status information regarding the buffer.
6. The method of claim 1 , further comprising:
determining to read the set of data from a memory array within the memory device based at least in part on the set of data being absent from the buffer, wherein the memory array comprises non-volatile memory cells; and
determining to send the indication of the time delay based at least in part on determining to read the set of data from the memory array.
7. A method, comprising:
receiving, from a host, a read command for a set of data at a memory device, wherein the memory device comprises content-addressable memory (CAM) and the read command comprises search data for the CAM;
determining that the set of data is absent from a buffer within the memory device, wherein determining that the set of data is absent from the buffer comprises determining that each memory cell of the CAM comprises a mismatch relative to the search data; and
sending, to the host, an indication of a time delay for the host to observe before issuing a subsequent access command based at least in part on the set of data being absent from the buffer.
8. A method, comprising:
receiving, from a host, a write command for a set of data;
determining a status of a buffer in a memory device, the memory device including the buffer and a memory array;
sending, to the host, an indication of a time delay for the host to observe before issuing a subsequent access command, the indication of the time delay being based at least in part on the status of the buffer, wherein sending the indication of the time delay for the host to observe comprises transmitting one or more pulses on a pin of the memory device, and wherein a duration of the time delay is indicated by a quantity of pulses, a pulse duration, or a pulse pattern, or any combination thereof.
9. The method of claim 8 , wherein determining the status of the buffer comprises:
determining an amount of available space in the buffer;
comparing the amount of available space to a threshold value; and
determining the status of the buffer based at least in part on comparing the amount of available space to the threshold value.
10. The method of claim 8 , wherein the indication of the time delay comprises an indication of an amount of available space in the buffer.
11. The method of claim 8 , wherein the time delay is based at least in part on a latency for writing a second set of data stored in the buffer to the memory array.
12. The method of claim 8 , further comprising:
determining the duration of the time delay based at least in part on the status of the buffer or a status of the memory array.
13. The method of claim 9 , further comprising:
determining the threshold value based at least in part on a size of the set of data or a size of a second set of data stored in the buffer, or any combination thereof.
14. An apparatus, comprising:
a first controller coupled with a buffer and with a memory array comprising non-volatile memory cells; and
a bus coupled with the first controller, the first controller configured to send an indication of a time delay associated with an access command received by the first controller via a pin in electronic communication with the bus and designated for command or control information, wherein the first controller is configured to send the indication of the time delay as comprising one or more pulses on the pin of the apparatus, and wherein the first controller is configured to indicate a duration of the time delay based at least in part on a quantity of pulses, a pulse duration, or a pulse pattern, or any combination thereof.
15. The apparatus of claim 14 , wherein the first controller is configured to determine the time delay based at least in part on availability in the buffer of data associated with a read command, availability in the buffer of space for data associated with a write command, or an activity level of the memory array, or any combination thereof.
16. The apparatus of claim 14 , further comprising:
a system on a chip (SoC) or processor coupled with the bus, the SoC or processor configured to, based at least in part on the indication of the time delay, observe a fixed wait period before issuing a subsequent access command.
17. The apparatus of claim 14 , further comprising:
a system on a chip (SoC) or processor coupled with the bus, the SoC or processor configured to, based at least in part on the indication of the time delay, observe a configurable wait period specified by the indication of the time delay before issuing a subsequent access command.
18. The apparatus of claim 14 , further comprising:
a control component coupled with the bus, the control component configured to determine an operational mode of the apparatus based at least in part on receiving the indication of the time delay.