Uniformity between levels of a multi-level signal
View Patent ↗Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
1. An apparatus, comprising:
a multi-leg driver that comprises a first plurality of legs coupled with a first resistive component and a second plurality of legs coupled with a second resistive component, wherein the first plurality of legs is configured to output first data that includes multiple bits and the second plurality of legs is configured to output second data that includes multiple bits;
a transmitter coupled with the first resistive component and the second resistive component of the multi-leg driver, the transmitter being configured to transmit the first data and the second data;
a controller coupled with the multi-leg driver, the controller being configured to determine an output impedance offset between the first transmitted data and the second transmitted data; and
a first transistor coupled with the transmitter, the first transistor configured to adjust a resistance level of at least one of the first plurality of legs based at least in part on the controller determining the output impedance offset between the first transmitted data and the second transmitted data.
2. The apparatus of claim 1 , further comprising:
a second transistor coupled with the transmitter, the second transistor being configured to adjust a resistance level of at least one of the second plurality of legs in response to the determination.
3. The apparatus of claim 2 , wherein the first transistor is a pull-up transistor and the second transistor is a pull-down transistor.
4. The apparatus of claim 2 , wherein the first transistor is configured to adjust an output impedance of the first plurality of legs of the multi-leg driver to a set impedance level.
5. The apparatus of claim 4 , wherein the second transistor is configured to adjust an output impedance of the second plurality of legs of the multi-leg driver to the set impedance level.
6. The apparatus of claim 4 , wherein the first transistor is configured to adjust the output impedance from the first plurality of legs of the multi-leg driver by enabling at least one leg of the first plurality of legs.
7. The apparatus of claim 4 , wherein the first transistor is configured to adjust the output impedance from the first plurality of legs of the multi-leg driver by disabling at least one leg of the first plurality of legs.
8. The apparatus of claim 3 , wherein the pull-up transistor is a PMOS transistor and the pull-down transistor is an NMOS transistor.
9. The apparatus of claim 3 , wherein the pull-up transistor and the pull-down transistor are NMOS transistors.
10. A method, comprising:
receiving first data and second data output from a transmitter coupled with a multi-leg driver, wherein the first data and the second data include multiple bits;
comparing the first data and the second data output from the transmitter;
determining an output impedance offset between the first data and the second data based at least in part on the comparison; and
initiating an adjustment of a resistance level of a first leg of the multi-leg driver to a second resistance level different than a first resistance level based at least in part on determining the output impedance offset between the first data and the second data, the initiated adjustment being performed by a transistor in electronic communication with the first leg.
11. The method of claim 10 , further comprising:
setting an output impedance of the first leg of the multi-leg driver based at least in part on the second resistance level.
12. The method of claim 10 , wherein the initiation of the adjustment of the first resistance level comprises enabling the first leg, wherein the first leg is associated with a most significant bit or a least significant bit.
13. The method of claim 10 , wherein the initiation of the adjustment of the first resistance level comprises disabling the first leg, wherein the first leg is associated with a most significant bit or a least significant bit.
14. The method of claim 10 , further comprising:
determining the output impedance offset between the first data and the second data after the adjustment to the second resistance level; and
initiating an adjustment of the second resistance level of the first leg to a third resistance level different than the second resistance level, wherein the initiation of the adjustment to the third resistance level is based at least in part on the determination of the output impedance offset after the adjustment to the second resistance level.
15. An apparatus, comprising:
a multi-leg driver that comprises a first leg group coupled with a first resistive component and a second leg group coupled with a second resistive component, wherein the first leg group is configured to output first data and the second leg group is configured to output second data;
a transmitter coupled with the first resistive component and the second resistive component, the transmitter being configured to output the first data and the second data;
a first transistor coupled with the transmitter; and
a controller coupled with the multi-leg driver, wherein the controller is operable to:
receive the first data and the second data output from the transmitter;
compare the first data and the second data output from the transmitter;
determine an output impedance offset between the first data and the second data in response to the comparison; and
initiate an adjustment of a resistance level of at least one leg of the first leg group of the multi-leg driver to a second resistance level different than a first resistance level based at least in part on determining the output impedance offset between the first data and the second data, the initiated adjustment being performed by the first transistor in electronic communication with at least one of the first plurality of legs.
16. The apparatus of claim 15 , wherein the controller is further operable to:
initiate an adjustment of a resistance level of at least one leg of the second leg group to a second resistance level different than a first resistance level based at least in part on the determination, wherein the second resistance level of the at least one leg of the first leg group and the second resistance level of the at least one leg of the second leg group are uniform.
17. The apparatus of claim 16 , wherein the adjusted resistance level of the at least one leg of the first leg group or the at least one leg of the second leg group is based at least in part on adjusting a resistance of the first transistor.
18. The apparatus of claim 15 , wherein the reception of the first data and the second data output from the transmitter further comprises:
measuring an amplitude of each of the first data and the second data.
19. The apparatus of claim 15 , wherein the initiation of the adjustment of the first resistance level of the at least one leg of the first leg group further comprises:
enabling the at least one leg of the first leg group based at least in part on the determined output impedance offset.
20. The apparatus of claim 15 , wherein the initiation of the adjustment of the first resistance level of the at least one leg of the first leg group further comprises:
disabling the at least one leg of the first leg group based at least in part on the determined output impedance offset.