Systems and methods for reducing coupling noise between propagation lines for die size efficiency

1. A memory device, comprising:

a memory array;

lower data terminals;

upper data terminals; and

an input/output (I/O) circuit including an internal, global data bus electrically coupling the lower and the upper data terminals to the memory array,

wherein—

the internal, global data bus includes a first plurality of global data lines corresponding to the lower data terminals and a second plurality of global data lines corresponding to the upper data terminals,

each global data line of the first plurality of global data lines and each global data line of the second plurality of global data lines corresponds to every memory cell of the memory array,

the second plurality of global data lines are directly interleaved between the first plurality of global data lines, and

the second plurality of global data lines are configured to shield the first plurality of global data lines.

2. The memory device of claim 1 further comprising a center, wherein the upper data terminals are located at a first location in the memory device, and wherein the lower data terminals are located at a second location in the memory device closer to the center of the memory device than the first location.

3. The memory device of claim 2 , wherein the first plurality of global data lines are shorter in length than the second plurality of global data lines.

4. The memory device of claim 1 , wherein the I/O circuit is configured to drive the second plurality of global data lines to a constant state when the second plurality of global data lines are not used to transfer data to and/or from the memory array.

5. The memory device of claim 4 , wherein the I/O circuit further includes a lower data mask terminal, an upper data mask terminal, a first plurality of data mask lines corresponding to the lower data mask terminal, and a second plurality of data mask lines corresponding to the upper data mask terminal, and wherein the I/O circuit is configured to force the second plurality of data mask lines to a high state to mask signals transmitted on the second plurality of global data lines.

6. The memory device of claim 1 , wherein the I/O circuit is configured to (i) switch the first plurality of global data lines at a first time when the second plurality of global data lines are not being switched and (ii) switch the second plurality of global data lines at a second time when the first plurality of global data lines are not being switched, and wherein the second time is after the first time.

7. The memory device of claim 6 , wherein the I/O circuit is further configured to pass signals transmitted on the first plurality of global data lines to repeaters at a center of the memory device to account for delay in reception of signals transmitted on the second plurality of global data lines, and wherein the delay in reception is due to larger lengths of the second plurality of global data lines than lengths of the first plurality of global data lines.

8. The memory device of claim 7 , wherein the I/O circuit further includes one or more buffers, and wherein the delay in reception is based at least in part on the one or more buffers.

9. The memory device of claim 6 , wherein the I/O circuit is configured to continuously switch the first and second pluralities of global data lines during burst read and/or burst write access modes.

10. The memory device of claim 1 further comprising DC shield lines, wherein the DC shield lines are located at edges of the internal, global data bus.

11. The memory device of claim 10 , wherein the DC shield lines are tied to one of a power supply and a ground such that the DC shield lines transmit a continuous, static signal.

12. A memory system, comprising:

a host device; and

a memory device including—

a memory array; and

an input/output (I/O) circuit including an internal, global data bus having a first plurality of global data lines and a second plurality of global data lines,

wherein—

each global data line of the first plurality of global data lines and each global data line of the second plurality of global data lines corresponds to every memory cell of the memory array,

the second plurality of global data lines are directly interleaved between the first plurality of global data lines, and

the second plurality of global data lines are configured to shield the first plurality of global data lines.

13. The memory system of claim 12 , wherein the first plurality of global data lines are shorter in length than the second plurality of global data lines.

14. The memory system of claim 13 , wherein the I/O circuit is configured to (i) switch the first plurality of global data lines at a first time when the second plurality of global data lines are not being switched and (ii) switch the second plurality of global data lines at a second time when the first plurality of global data lines are not being switched, and wherein the second time is after the first time.

15. The memory system of claim 14 , wherein the I/O circuit is further configured to pass signals transmitted on the first plurality of global data lines to repeaters at a center of the memory device to account for delay in reception of signals transmitted on the second plurality of global data lines, and wherein the delay in reception is due to the larger lengths of the second plurality of global data lines than the lengths of the first plurality of global data lines.

16. The memory system of claim 12 , wherein the internal global data bus further includes DC shield lines at edges of the internal, global data bus, and wherein the DC shield lines are tied to one of a power supply and a ground such that the DC shield lines transmit a continuous, static signal.

17. An input/output (I/O) circuit for use in a memory device, the I/O circuit comprising an internal, global data bus including a first plurality of global data lines and a second plurality of global data lines, wherein—

each global data line of the first plurality of global data lines and each global data line of the second plurality of global data lines corresponds to every memory cell of a memory array of the memory device;

the second plurality of global data lines are directly interleaved between the first plurality of global data lines; and

the second plurality of global data lines are configured to shield the first plurality of global data lines.

18. The I/O circuit of claim 17 , wherein the I/O circuit is configured to drive the second plurality of global data lines to a constant state when the second plurality of global data lines are not used to transfer data.

19. The I/O circuit of claim 17 , wherein the I/O circuit is configured to (i) switch the first plurality of global data lines at a first time when the second plurality of global data lines are not being switched and (ii) switch the second plurality of global data lines at a second time when the first plurality of global data lines are not being switched, and wherein the second time is after the first time.

20. The I/O circuit of claim 17 , wherein the internal, global data bus further includes DC shield lines at edges of the internal, global data bus, and wherein the DC shield lines are tied to one of a power supply and a ground such that the DC shield lines transmit a continuous, static signal.