A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.
1. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising a transistor and a capacitor, one of (a) a channel region of the transistor, or (b) a pair of electrodes of the capacitor, being directly above the other of (a) and (b); and
a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the capacitor-electrode structure electrically coupling together one electrode of individual of the pairs of electrodes that are in different memory cell tiers.
2. The array of claim 1 wherein the channel region is directly above the pair of electrodes.
3. The array of claim 1 wherein the pair of electrodes is directly above the channel region.
4. The array of claim 1 wherein the transistor comprises first and second source/drain regions neither of which is directly above the other.
5. The array of claim 1 wherein the transistor comprises first and second source/drain regions one of which is above the other.
6. The array of claim 5 wherein neither of the first and second source/drain regions is directly above the other.
7. The array of claim 1 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through.
8. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor and a capacitor, one of (a) a channel region of the transistor, or (b) a pair of electrodes of the capacitor, being directly above the other of (a) and (b); and
the transistor comprising first and second source/drain regions having the channel region there-between, the first and second source/drain regions and the channel region collectively comprising opposing C-like shapes that face one another in a straight-line vertical cross-section.
9. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor and a capacitor, one of (a) a channel region of the transistor, or (b) a pair of electrodes of the capacitor, being directly above the other of (a) and (b); and
at least one electrode of the pair comprising opposing C-like shapes that face one another in a straight-line vertical cross-section.
10. The array of claim 1 wherein the channel region comprises an annulus in a straight-line horizontal cross-section.
11. The array of claim 1 wherein at least one of the pair of electrodes comprises an annulus in a straight-line horizontal cross-section.
12. The array of claim 1 wherein the transistor comprises a gate, the gate comprising an annulus in a straight-line horizontal cross-section.
13. A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor and a capacitor, one of (a) a channel region of the transistor, or (b) a pair of electrodes of the capacitor, being directly above the other of (a) and (b);
the transistor comprising a gate, the gate comprising an annulus in a straight-line horizontal cross-section; and
a plurality of the gates in individual of the tiers of memory cells being directly electrically coupled to one another along a conductive line, the annuli of immediately-laterally-adjacent of the gates overlapping one another in the line.
14. A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another; and
one of (a) the channel region of the transistor, or (b) the first and second electrodes of the capacitor, being directly above the other of (a) and (b); and
a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure.
15. The array of claim 14 wherein the sense-line structure is directly electrically coupled to a horizontal longitudinally-elongated sense line that is above or below the vertically-alternating tiers.
16. The array of claim 14 wherein the sense-line structure comprises a pillar.
17. A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; and
one of (a) the channel region of the transistor, or (b) the first and second electrodes of the capacitor, being directly above the other of (a) and (b);
a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure; and
a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers.
18. The array of claim 17 wherein the sense-line structure comprises a pillar.
19. The array of claim 17 comprising at least one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the individual second electrodes of the individual capacitors that are in different memory cell tiers being electrically coupled to the at least one more elevationally-extending capacitor-electrode structure.
20. The array of claim 19 comprising more than one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers.
21. The array of claim 20 wherein the capacitor-electrode structures are circumferentially spaced about the first electrode.
22. The array of claim 21 wherein the capacitor-electrode structures total six in number.
23. The array of claim 17 wherein the capacitor-electrode structure is directly electrically coupled to a horizontally-elongated capacitor-electrode construction that is above or below the vertically-alternating tiers.
24. A memory array, comprising:
vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; and
one of (a) the channel region of the transistor, or (b) the first and second electrodes of the capacitor, being directly above the other of (a) and (b);
a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure; and
a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure.
25. The array of claim 24 comprising at least one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the individual second electrodes of the individual capacitors being electrically coupled to the at least one more elevationally-extending capacitor-electrode structure.
26. The array of claim 25 comprising more than one more capacitor-electrode structure extending elevationally through the vertically-alternating tiers, the capacitor-electrode structures being circumferentially spaced about the first electrode.
27. The array of claim 24 wherein the gate comprises an annulus in a straight-line horizontal cross-section, a plurality of the gates in individual of the tiers of memory cells being directly electrically coupled to one another along a conductive line, the annuli of immediately-laterally-adjacent of the gates overlapping one another in the line.