Semiconductor devices having discretely located passivation material, and associated systems and methods
View Patent ↗Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
1. A semiconductor device assembly, comprising:
a semiconductor die including—
a bond pad having a bonding surface, wherein the bonding surface includes a process artifact; and
a passivation material at least partially filling a portion of the process artifact; and
a conductive structure extending across the bonding surface of the bond pad.
2. The semiconductor device assembly of claim 1 wherein the process artifact comprises a probe scrub mark forming an overhanging portion on the bonding surface of the bond pad, and wherein the passivation material at least partially underfills the overhanging portion.
3. The semiconductor device assembly of claim 1 wherein the process artifact comprises a probe scrub mark forming a crevice on the bonding surface of the bond pad, and wherein the passivation material at least partially fills the crevice.
4. The semiconductor device assembly of claim 1 wherein the passivation material is dielectric, and wherein the process artifact includes a brow forming a void.
5. The semiconductor device assembly of claim 1 wherein the passivation material is dielectric, and wherein the process artifact includes a furrow forming a void.
6. The semiconductor device assembly of claim 1 wherein the process artifact comprises a probe scrub mark extending across a portion of the bonding surface of the bond pad, and wherein the passivation material is dielectric and is contained within the portion of the surface of the bond pad.
7. The semiconductor device assembly of claim 1 wherein the conductive structure includes an adhesion material and a seed material, wherein the adhesion material extends across the bonding surface, wherein the seed material extends across the adhesion material, and wherein a conductive interconnect extends from the seed material.
8. The semiconductor device assembly of claim 1 wherein the bond pad is an aluminum bond pad, and wherein the passivation material includes silicon oxide (Al x Si y O z ).
9. The semiconductor device assembly of claim 1 wherein the bond pad is an aluminum bond pad, and wherein the passivation material includes aluminum silicon oxide (Al x Si y O z ), aluminum oxide (Al x1 O y1 ), and silicon oxide (Si x2 O y2 ).
10. The semiconductor device assembly of claim 1 wherein the die is a first die and the bond pad is a first bond pad, the semiconductor device assembly further comprising a second die having a second bond pad, and wherein a conductive interconnect is disposed between the first bond pad and the second bond pad to provide an electrical connection therebetween.
11. A semiconductor device assembly, comprising:
a die having a bonding element, a passivation material, and one or more conductive materials, wherein the bonding element includes a bonding surface having a probe scrub mark, wherein the probe scrub mark extends across a portion of the bonding surface, wherein the passivation material is contained within the portion of the bonding surface, and wherein the one or more conductive materials extend across the bonding surface.
12. The semiconductor device assembly of claim 11 , further comprising a pillar extending from the one or more conductive materials, wherein the pillar includes a base defining a footprint overlying the portion of the bonding surface.
13. The semiconductor device assembly of claim 12 wherein the die is a first die, wherein the semiconductor device assembly further includes a second die, and wherein the pillar provides an electrical connection between the first die and the second die.
14. The semiconductor device assembly of claim 11 wherein the bonding element is an aluminum bond pad, and the passivation material includes aluminum silicon oxide (Al x Si y O z ).
15. The semiconductor device assembly of claim 11 wherein the probe scrub mark defines a plurality of voids in the bonding surface, and wherein the passivation material is at least partially positioned within the voids.
16. The semiconductor device assembly of claim 11 wherein the probe scrub mark includes a brow forming a void, and wherein the passivation material at least partially fills the void.
17. The semiconductor device assembly of claim 11 wherein the probe scrub mark includes a furrow forming a void, and wherein the passivation material at least partially fills the void.
18. The semiconductor device assembly of claim 11 wherein the probe scrub mark includes a crevice in the bonding surface, and wherein the passivation material at least partially fills the crevice.
19. The semiconductor device assembly of claim 11 wherein the portion of the bonding surface comprises less than half of the bonding surface.
20. A method of forming a semiconductor device assembly, comprising
forming a passivation material on the bond pad of a semiconductor die, wherein the bond pad includes a probe scrub mark, wherein the passivation material overlies the bond pad and at least partially fills the probe scrub mark;
etching away at least some of the passivation material not overlying the probe scrub mark; and
forming a conductive structure that extends across the bond pad and covers the probe scrub mark.
21. The method of claim 20 wherein forming the passivation material includes applying a solution to the semiconductor die, wherein the solution includes tetramethyl ammonium hydroxide, silicon and ammonium persulfate.
22. The method of claim 21 wherein the mass/volume percentage of the tetramethyl ammonium hydroxide in the solution is 8 to 10 percent, the mass/volume percentage of the silicon in the solution is 1.5 to 3 percent, and the mass/volume percentage of the ammonium persulfate in the solution is 2 to 2.5 percent.
23. The method of claim 22 wherein applying the solution to the semiconductor die includes maintaining the solution at a temperature of 68 to 82 degrees Celcius, and immersing the die in the solution.
24. The method of claim 20 wherein forming the passivation material includes forming an aluminum silicon oxide (Al x Si y O z ).
25. The method of claim 20 wherein forming the passivation material includes growing an oxide on a surface of the bond pad.
26. The method of claim 20 , further comprising forming a conductive interconnect on the conductive structure, wherein the conductive interconnect overlies the probe scrub mark.
27. The method of claim 26 wherein forming the conductive structure includes forming a titanium material that extends across the bond pad and forming a copper material that extends across the titanium material, and wherein forming the conductive interconnect includes forming the conductive interconnect on the copper material.