IP Library Granted Patent US 10,951,239
Granted Patent B2
US 10,951,239 · App. 15/900,562 · Granted Mar 16, 2021

Performing a decoding operation to simulate switching a bit of an identified set of bits of a data block

Inventors: Yingquan Wu (Palo Alto, CA); Eyal En Gad (Santa Clara, CA)
Assignee: MICRON TECHNOLOGY, INC.
H03M13/3738G06F11/1012G06F11/1068G11C29/52H03M13/3707
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Quick Facts
Patent No.
US 10,951,239
App. No.
15/900,562
Granted
Mar 16, 2021
Kind
B2
Abstract

A set of bits of a data block that is associated with an unsuccessful first decoding operation may be identified. A second decoding operation to simulate switching at least one bit of the set of bits may be performed. At least one bit of the set of bits switched during the performance of the second decoding operation may be determined to correspond to an error. The error from the at least one bit of the set of bits may be corrected by changing a value of the at least one bit.

Claims (41)

1. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to:

identify a set of bits of a data block that is associated with an unsuccessful first decoding operation, the set of bits comprising a first number of bits corresponding to an intersection of a row and a column of the data block and having an associated number of errors that exceeds an error correction capability of the first decoding operation;

perform a second decoding operation, wherein the second decoding operation comprises a first number of iterations equal to the first number of bits in the set of bits, and wherein a only one bit of the set of bits comprising the first number of bits is switched during each iteration of the first number of iterations of the second decoding operation to identify one or more bit locations in the set of bits comprising the first number of bits corresponding to the associated number of errors;

determine whether the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to a bit-flip error; and

in response to determining that the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to the bit-flip error, correct the bit-flip error for the one bit of the set of bits by changing a value of the at least one bit.

2. The system of claim 1 , wherein determining whether the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to the bit-flip error is based on outputs of the unsuccessful first decoding operation.

3. The system of claim 1 , wherein identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation is in response to performing a first decoding operation on the data block.

4. The system of claim 1 , wherein the data block is associated with a plurality of rows and a plurality of columns, and wherein to identify the set of bits of the data block that is associated with the unsuccessful first decoding operation, the processing device is further to:

determine the row of the plurality of rows of the data block that is associated with the unsuccessful first decoding operation; and

determine the column of the plurality of columns of the data block that is associated with the unsuccessful first decoding operation.

5. The system of claim 1 , wherein identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation is based on at least one status bit corresponding to the set of bits of the data block indicating the unsuccessful first decoding operation.

6. The system of claim 1 , wherein the processing device is further to:

in response to correcting the bit-flip error from the one bit of the set of bits, identify a code word associated with the corrected set of bits of the data block.

7. A method comprising:

identifying a set of bits of a data block that is associated with an unsuccessful first decoding operation, the set of bits comprising a first number of bits corresponding to an intersection of a row and a column of the data block and having an associated number of errors that exceeds an error correction capability of the first decoding operation;

performing a second decoding operation, wherein the second decoding operation comprises a first number of iterations equal to the first number of bits in the set of bits, and wherein a only one bit of the set of bits comprising the first number of bits is switched during each iteration of the first number of iterations of the second decoding operation to identify one or more bit locations in the set of bits comprising the first number of bits corresponding to the associated number of errors;

determining, by a processing device, whether the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to a bit-flip error; and

in response to determining that the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to the bit-flip error, correcting the bit-flip error for the one bit of the set of bits by changing a value of the one bit.

8. The method of claim 7 , wherein determining whether the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to the bit-flip error is based on outputs of the unsuccessful first decoding operation.

9. The method of claim 7 , wherein the identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation is in response to performing a first decoding operation on the data block.

10. The method of claim 7 , wherein the data block comprises a plurality of rows and a plurality of columns, and wherein identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation further comprises:

determining the row of the plurality of rows of the data block that is associated with the unsuccessful first decoding operation; and

determining the column of the plurality of columns of the data block that is associated with the unsuccessful first decoding operation.

11. The method of claim 7 , wherein identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation is based on at least one status bit corresponding to the set of bits of the data block indicating the unsuccessful first decoding operation.

12. The method of claim 7 , further comprising:

in response to correcting the bit-flip error from the one bit of the set of bits, identifying a code word associated with the corrected set of bits of the data block.

13. A non-transitory computer readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

identifying a set of bits of a data block that is associated with an unsuccessful first decoding operation, the set of bits comprising a first number of bits corresponding to an intersection of a row and a column of the data block and having an associated number of errors that exceeds an error correction capability of the first decoding operation;

performing a second decoding operation, wherein the second decoding operation comprises a first number of iterations equal to the first number of bits in the set of bits, and wherein a only one bit of the set of bits comprising the first number of bits is switched during each iteration of the first number of iterations of the second decoding operation to identify one or more bit locations in the set of bits comprising the first number of bits corresponding to the associated number of errors;

determining, by a processing device, whether the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to a bit-flip error; and

in response to determining that the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to the bit-flip error, correcting the bit-flip error for the one bit of the set of bits by changing a value of the one bit.

14. The non-transitory computer readable storage medium of claim 13 , wherein determining whether the one bit of the set of bits switched during each iteration of the second decoding operation corresponds to the bit-flip error is based on outputs of the unsuccessful first decoding operation.

15. The non-transitory computer readable storage medium of claim 13 , wherein the identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation is in response to performing a first decoding operation on the data block.

16. The non-transitory computer readable storage medium of claim 13 , wherein the data block comprises a plurality of rows and a plurality of columns, and wherein identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation further comprises:

determining the row of the plurality of rows of the data block that is associated with the unsuccessful first decoding operation; and

determining the column of the plurality of columns of the data block that is associated with the unsuccessful first decoding operation.

17. The non-transitory computer readable storage medium of claim 13 , wherein identifying the set of bits of the data block that is associated with the unsuccessful first decoding operation is based on at least one status bit corresponding to the set of bits of the data block indicating the unsuccessful first decoding operation.

18. The non-transitory computer readable storage medium of claim 13 , further comprising:

in response to correcting the bit-flip error from the one bit of the set of bits, identifying a code word associated with the corrected set of bits of the data block.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2018
From: WU, YINGQUAN; GAD, EYAL EN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044982/0181 →
Continuity (1)
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