Memory devices having selectively electrically connected data lines
Memory devices may include a first string of memory cells selectively electrically connected to a first data line and a second string of memory cells selectively electrically connected to a second data line, wherein the first data line and the second data line are selectively electrically connected with no intervening memory cells, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.
1. A memory device, comprising:
a first string of memory cells selectively electrically connected to a first data line;
a second string of memory cells selectively electrically connected to a second data line; and
a transistor that selectively electrically connects the first data line to the second data line with no intervening memory cells between the first transistor and the first data line and no intervening memory cells between the first transistor and the second data line.
2. The memory device of claim 1 , further comprising plurality of page buffers electrically connected in series with the second data line.
3. The memory device of claim 2 , wherein respective ones of at least a portion of the plurality of page buffers are respectively used for different ones of a first number of bits of data for a memory cell in either the first string or the second string when the memory device is operating the first string and the second string in a first mode of operation, and wherein, when the memory device is operating the first string and the second string in a second mode of operation, respective ones of one or more page buffers of the plurality of page buffers are respectively used for respective ones of one or more bits of data for a memory cell in the first string and respective ones of one or more other page buffers of the plurality of page buffers are respectively used for respective ones of one or more bits of data for a memory cell in the second string, wherein the first number of bits is greater than a number of the one or more bits of the data for the memory cell in the first string and a number of the one or more bits of the data for the memory cell in the second string.
4. The memory device of claim 1 , further comprising a sense amplifier electrically connected in series with the second data line.
5. The memory device of claim 1 , further comprising a data latch electrically connected in series with the second data line.
6. The memory device of claim 1 , wherein the transistor is a first transistor, wherein the first string is electrically connected between a second transistor that selectively electrically connects the first string to a first source and a third transistor that selectively electrically connects the first string to the first data line, and wherein the second string is electrically connected between a fourth transistor that selectively electrically connects the second string to a second source and a fifth transistor that selectively electrically connects the second string to the second data line.
7. The memory device of claim 1 , wherein the first string is a vertical string in a first portion of a stacked memory array and the second string is a vertical string in a second portion of the stacked memory array.
8. The memory device of claim 7 , wherein the transistor is between first and second portions of the stacked memory array.
9. The memory device of claim 7 , wherein the transistor is directly vertically below the second portion of the stacked memory array.
10. The memory device of claim 9 , wherein the transistor is electrically connected to the second data line between where the second string of memory cells is selectively electrically connected to the second data line and where an adjacent string of memory cells is selectively electrically connected to the second data line.
11. A memory device, comprising:
a first string of memory cells selectively electrically connected to a first data line;
a second string of memory cells selectively electrically connected to a second data line;
a first transistor electrically connected in series with the first data line; and
a second transistor electrically connected in series with the second data line and the first transistor with no intervening memory cells between the first transistor and the second transistor.
12. The memory device of claim 11 , further comprising a plurality of page buffers electrically connected to a node between the first transistor and the second transistor.
13. The memory device of claim 12 , wherein the first transistor selectively electrically connects the plurality of page buffers in parallel to the first data line and the second transistor selectively electrically connects the plurality of page buffers in parallel to the second data line.
14. The memory device of claim 12 , wherein respective ones of at least a portion of the plurality of page buffers are respectively used for different ones of a first number of bits of data for a memory cell in either the first string or the second string when the memory device is operating the first string and the second string in a first mode of operation, and wherein, when the memory device is operating the first string and the second string in a second mode of operation, respective ones of one or more page buffers of the plurality of page buffers are respectively used for respective ones of one or more bits of data for a memory cell in the first string and respective ones of one or more other page buffers of the plurality of page buffers are respectively used for respective ones of one or more bits of data for a memory cell in the second string, wherein the first number of bits is greater than a number of the one or more bits of the data for the memory cell in the first string and a number of the one or more bits of the data for the memory cell in the second string.
15. The memory device of claim 11 , further comprising a sense amplifier electrically connected to a node between the first transistor and the second transistor.
16. The memory device of claim 11 , further comprising a data latch electrically connected to a node between the first transistor and the second transistor.
17. The memory device of claim 11 , wherein the first string is electrically connected between a third transistor that selectively electrically connects the first string to a first source and a fourth transistor that selectively electrically connects the first string to the first data line, and wherein the second string is electrically connected between a fifth transistor that selectively electrically connects the second string to a second source and a sixth transistor that selectively electrically connects the second string to the second data line.
18. A memory device, comprising:
a first string of memory cells selectively electrically connected to a first data line;
a second string of memory cells selectively electrically connected to a second data line;
a transistor that selectively electrically connects the first data line to the second data line with no intervening memory cells between the first transistor and the first data line and no intervening memory cells between the first transistor and the second data line; and
a sense amplifier, a plurality of page buffers, and a data latch electrically connected in series with the second data line.
19. The memory device of claim 18 , wherein first and second page buffers of the plurality of page buffers are respectively used to receive respective ones of two bits to be programmed to a memory cell of the first string of memory cells when the memory cells of the first string of memory cells are operating as two-bit memory cells, and wherein the first and second page buffers of the plurality of page buffers are respectively used to receive one bit to be programmed to the memory cell of the first string of memory cells and one bit to be programmed to a memory cell of the second string of memory cells when the memory cells of the first and second strings of memory cells are operating as single-bit memory cells.
20. The memory device of claim 18 , wherein first and second page buffers of the plurality of page buffers are respectively used to receive respective ones of two bits read from a memory cell of the first string of memory cells when the memory cells of the first string of memory cells are operating as two-bit memory cells, and wherein the first and second page buffers of the plurality of page buffers are respectively used to receive one bit read from the memory cell of the first string of memory cells and one bit read from a memory cell of the second string of memory cells when the memory cells in the first and second strings of memory cells are operating as single-bit memory cells.