Sense amplifier constructions
View Patent ↗A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.
1. A sense amplifier construction comprising:
a first n-type transistor and a second n-type transistor vertically offset above the first n-type transistor;
a third p-type transistor and a fourth p-type transistor vertically offset above the third p-type transistor;
a lower voltage activation line electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors; and
a higher voltage activation line electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.
2. The sense amplifier construction of claim 1 wherein the first, second, third, and fourth transistors are each vertical or within 10° of vertical.
3. The sense amplifier construction of claim 1 wherein the sense amplifier is a latch-based sense amplifier.
4. The sense amplifier construction of claim 1 wherein the sense amplifier is a differential voltage sense amplifier.
5. The sense amplifier construction of claim 1 wherein the first, second, third, and fourth transistors are each vertical.
6. The sense amplifier construction of claim 1 wherein the lower voltage activation line and the higher voltage activation line are laterally offset relative one another.
7. The sense amplifier construction of claim 6 wherein the lower voltage activation line and the higher voltage activation line are elevationally coincident relative one another.
8. The sense amplifier construction of claim 1 wherein the first n-type transistor and the third p-type transistor are laterally offset relative one another.
9. The sense amplifier construction of claim 8 wherein the first n-type transistor and the third p-type transistor are elevationally coincident relative one another.
10. The sense amplifier construction of claim 1 wherein the second n-type transistor and the fourth p-type transistor are laterally offset relative one another.
11. The sense amplifier construction of claim 10 wherein the second n-type transistor and the fourth p-type transistor are elevationally coincident relative one another.